• Title/Summary/Keyword: Information input algorithm

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Power Decoupling Control of the Bidirectional Converter to Eliminate the Double Line Frequency Ripple (더블라인 주파수 제거를 위한 양방향 컨버터의 전력 디커플링 제어)

  • Amin, Saghir;Choi, Woojin
    • Proceedings of the KIPE Conference
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    • 2018.11a
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    • pp.62-64
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    • 2018
  • In two-stage single-phase inverters, inherent double line frequency component is present at both input and output of the front-end converter. Generally large electrolytic capacitors are required to eliminate the ripple. It is well known that the low frequency ripple shortens the lifespan of the capacitor hence the system reliability. However, the ripple can hardly be eliminated without the hardware combined with an energy storage device or a certain control algorithm. In this paper, a novel power-decoupling control method is proposed to eliminate the double line frequency ripple at the front-end converter of the DC/AC power conversion system. The proposed control algorithm is composed of two loop, ripple rejection loop and average voltage control loop and no extra hardware is required. In addition, it does not require any information from the phase-locked-loop (PLL) of the inverter and hence it is independent of the inverter control. In order to prove the validity and feasibility of the proposed algorithm a 5kW Dual Active Bridge DC/DC converter and a single-phase inverter are implemented, and experimental results are presented.

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EXTRACTION OF THE LEAN TISSUE BOUNDARY OF A BEEF CARCASS

  • Lee, C. H.;H. Hwang
    • Proceedings of the Korean Society for Agricultural Machinery Conference
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    • 2000.11c
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    • pp.715-721
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    • 2000
  • In this research, rule and neuro net based boundary extraction algorithm was developed. Extracting boundary of the interest, lean tissue, is essential for the quality evaluation of the beef based on color machine vision. Major quality features of the beef are size, marveling state of the lean tissue, color of the fat, and thickness of back fat. To evaluate the beef quality, extracting of loin parts from the sectional image of beef rib is crucial and the first step. Since its boundary is not clear and very difficult to trace, neural network model was developed to isolate loin parts from the entire image input. At the stage of training network, normalized color image data was used. Model reference of boundary was determined by binary feature extraction algorithm using R(red) channel. And 100 sub-images(selected from maximum extended boundary rectangle 11${\times}$11 masks) were used as training data set. Each mask has information on the curvature of boundary. The basic rule in boundary extraction is the adaptation of the known curvature of the boundary. The structured model reference and neural net based boundary extraction algorithm was developed and implemented to the beef image and results were analyzed.

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Hand Gesture Recognition Algorithm Robust to Complex Image (복잡한 영상에 강인한 손동작 인식 방법)

  • Park, Sang-Yun;Lee, Eung-Joo
    • Journal of Korea Multimedia Society
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    • v.13 no.7
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    • pp.1000-1015
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    • 2010
  • In this paper, we propose a novel algorithm for hand gesture recognition. The hand detection method is based on human skin color, and we use the boundary energy information to locate the hand region accurately, then the moment method will be employed to locate the hand palm center. Hand gesture recognition can be separated into 2 step: firstly, the hand posture recognition: we employ the parallel NNs to deal with problem of hand posture recognition, pattern of a hand posture can be extracted by utilize the fitting ellipses method, which separates the detected hand region by 12 ellipses and calculates the white pixels rate in ellipse line. the pattern will be input to the NNs with 12 input nodes, the NNs contains 4 output nodes, each output node out a value within 0~1, the posture is then represented by composed of the 4 output codes. Secondly, the hand gesture tracking and recognition: we employed the Kalman filter to predict the position information of gesture to create the position sequence, distance relationship between positions will be used to confirm the gesture. The simulation have been performed on Windows XP to evaluate the efficiency of the algorithm, for recognizing the hand posture, we used 300 training images to train the recognizing machine and used 200 images to test the machine, the correct number is up to 194. And for testing the hand tracking recognition part, we make 1200 times gesture (each gesture 400 times), the total correct number is 1002 times. These results shows that the proposed gesture recognition algorithm can achieve an endurable job for detecting the hand and its' gesture.

The Obstacle Avoidance Algorithm of Mobile Robot using Line Histogram Intensity (Line Histogram Intensity를 이용한 이동로봇의 장애물 회피 알고리즘)

  • 류한성;최중경;구본민;박무열;방만식
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.6 no.8
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    • pp.1365-1373
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    • 2002
  • In this paper, we present two types of vision algorithm that mobile robot has CCD camera. for obstacle avoidance. This is simple algorithm that compare with grey level from input images. Also, The mobile robot depend on image processing and move command from PC host. we has been studied self controlled mobile robot system with CCD camera. This system consists of digital signal processor, step motor, RF module and CCD camera. we used wireless RF module for movable command transmitting between robot and host PC. This robot go straight until recognize obstacle from input image that preprocessed by edge detection, converting, thresholding. And it could avoid the obstacle when recognize obstacle by line histogram intensity. Host PC measurement wave from various line histogram each 20 pixel. This histogram is (x, y) value of pixel. For example, first line histogram intensity wave from (0, 0) to (0, 197) and last wave from (280, 0) to (2n, 197. So we find uniform wave region and nonuniform wave region. The period of uniform wave is obstacle region. we guess that algorithm is very useful about moving robot for obstacle avoidance.

Fast Matching Pursuit based on Vector Length Comparison (벡터길이 비교를 이용한 고속 Matching Pursuit)

  • O, Seok-Byeong;Jeon, Byeong-U
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.38 no.2
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    • pp.129-137
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    • 2001
  • Matching pursuit algorithm was successfully demonstrated useful in low bit-rate video coding, However, one of the practical concerns related to applying the matching pursuit algorithm to application is its massive computation required for finding bases whose weighted sum best approximates the given input image. The main contribution of this paper is that we provide a new method that can drastically reduce the computational load without any degradation of image quality. Its main idea is based on reducing the number of inner product calculation required for finding best bases because the complexity of matching pursuit algorithm is due to the exhaustive local inner product calculation. As the first step, we compute a matrix which is the 1-D inner product of the given motion-compensated error input image with the 1-D vertical Gabor functions using the separable property of Gabor bases. In the second step, we calculate length of each vector in the matrix that corresponds to 1-D horizontal Gabor function, and compare the length with the current maximum absolute inner product value so far. According to the result of this comparison, one can decide whether or not to calculate the inner product. Since most of them do not need to calculate the inner product value, one can significantly reduce the computational load. Experimental results show that proposed method reduces about 70% of inner product calculation compared to the Neff's fast algorithm without any degradation of image quality.

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A Study on the Convergence Characteristics Improvement of the Modified-Multiplication Free Adaptive Filer (변형 비적 적응 필터의 수렴 특성 개선에 관한 연구)

  • 김건호;윤달환;임제탁
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.18 no.6
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    • pp.815-823
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    • 1993
  • In this paper, the structure of modified multiplication-free adaptive filter(M-MADF) and convergence analysis are presented. To evaluate the performance of proposed M-MADF algorithm, fractionally spaced equalizer (FSE) is used. The input signals are quantized using DPCM and the reference signals is processed using a first-order linear prediction filter, and the outputs are processed by a conventional adaptive filter. The filter coefficients are updated using the Sign algorithm. Under the assumption that the primary and reference signals are zero mean, wide-sense stationary and Gaussian, theoretical results for the coefficient misalignment vector and its autocorrelation matrix of the filter are driven. The convergence properties of Sign. MADF and M-MADF algorithm for updating of the coefficients of a digital filter of the fractionally spaced equalizer (FSE) are investigated and compared with one another. The convergence properties are characterized by the steady state error and the convergence speed. It is shown that the convergence speed of M-MADF is almost same as Sign algorithm and is faster that MADF in the condition of same steady error. Especially it is very useful for high correlated signals.

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Efficient Hardware Design of Hash Processor Supporting SHA-3 and SHAKE256 Algorithms (SHA-3과 SHAKE256 알고리듬을 지원하는 해쉬 프로세서의 하드웨어 설계)

  • Choi, Byeong-Yoon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.6
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    • pp.1075-1082
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    • 2017
  • This paper describes a design of hash processor which can execute new hash algorithm, SHA-3 and extendable-output function (XOF), SHAKE-256. The processor that consists of padder block, round-core block and output block maximizes its performance by using the block-level pipelining scheme. The padder block formats the variable-length input data into multiple blocks and then round block generates SHA-3 message digest or SHAKE256 result for multiple blocks using on-the-fly round constant generator. The output block finally transfers the result to host processor. The hash processor that is implemented with Xilinx Virtex-5 FPGA can operate up to 220-MHz clock frequency. The estimated maximum throughput is 5.28 Gbps(giga bits per second) for SHA3-512. Because the processor supports both SHA-3 hash algorithm and SHAKE256 algorithm, it can be applicable to cryptographic areas such as data integrity, key generation and random number generation.

A design of Space Compactor for low overhead in Built-In Self-Test (내장 자체 테스트의 low overhead를 위한 공간 압축기 설계)

  • Jung, Jun-Mo
    • The Transactions of the Korea Information Processing Society
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    • v.5 no.9
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    • pp.2378-2387
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    • 1998
  • This thesis proposes a design algorithm of an efficient space response compactor for Built-In Self-Testing of VLSI circuits. The proposed design algorithm of space compactors can be applied independently from the structure of Circuit Cnder Test. There are high hardware overhead cost in conventional space response compactors and the fault coverage is reduced by aliasing which maps faulty circuit's response to fault-free one. However, the proposed method designs space response compactors with reduced hardware overheads and does not reduce the fault coverage comparing to conventional method. Also, the proposed method can be extended to general N -input logic gate and design the most efficient space response L'Ompactors according to the characteristies of output sequence from CUT. The prolxlsed design algorithm is implemented by C language on a SUN SPARC Workstation, and some experiment results of the simulation applied to ISCAS'85 benchmark circuits with pseudo random patterns generated bv LFSR( Linear Feedback Shift Register) show the efficiency and validity of the proposed design algorithm.

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A study on Identifying Undetectable Faults Using Uninitializable Flip-Flops (초기화가 불가능한 풀립플롭을 이용한 시험 불가능 고장 검출에 관한 연구)

  • Lee, Jae-Hun;Jo, Jin-U
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.5
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    • pp.1371-1379
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    • 1997
  • Undetectable faults in a digital circuit are faults that no input patterms can detect.Identifying these faults in test geferation process is very time- consuming especially for sequential circuits .In this paper we present a new algorithm to identify unedtectable faults in sequential cirouits .In the alorithm. we identify uninitializable fip-flops and then, faults that prevent intialization of the fkip-flops(FPIs)are identified, finally propagation path of the FPI is checked. Time complexity of this algorithm is porportional to the product of the number of flip flops with at lest a self loop and the number of gates in the circuit. Experiments were performed on the ISCAS89 benchmark ciruits to show the feadibility of the proposed algorithm.We could identify large amount of undetectable faults(up to 50% of the number of flip-flops)in circuits with uninitializable flip-flops. Consider-ing that most of the time in test generation is cinsumed in identifying undetecatable faults, performance of test generator can be improved by using this algorithm as a pre-processing of test generation.

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Vertical Sectorization Techniques in MISO Downlink Active Antenna Systems (MISO 하향 능동 안테나 시스템에서의 수직 섹터분할 기법)

  • Ahn, Minki;Eom, Subin;Lee, Inkyu
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.40 no.6
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    • pp.997-1004
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    • 2015
  • In this paper, we study vertical sectorization techniques in multiple-input single-output (MISO) downlink active antenna systems (AAS). In the AAS, antenna beam patterns can be adjusted in each sector and multiple vertical beams can form the vertical sectorization. Since an exhaustive search based vertical sectorization algorithm requires high computational complexity to find the optimal tilt angles, we propose two vertical sectorization algorithms to reduce the complexity. First, we provide an asymptotic sum rate based algorithm which utilizes a large system approximation of the average sum rate based on the random matrix theory. Next, by using the result in the single sector transmission, the single sector based algorithm is proposed. In the simulation results, we confirm that the proposed algorithms are close to the performance of the exhaustive search algorithm with much reduced complexity.