• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.10
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• pp.876-884
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• 2012

This paper introduces two multi-hop delay factors which can be caused by conventional TDMA scheduling; queueing delay and delay by random link scheduling, and proposes a new sequential scheduling scheme to resolve these two factors. We also simulate the TDMA network with the proposed link scheduling scheme and compare it with conventional(random) link scheduling scheme in terms of end-to-end packet transmission delay. From the simulation results, the more the average hop distance increases, the more the difference of the delay performance of both scheduling schemes increases. When the average number of hops is 2.66, 4.1, 4.75, and 6.3, the proposed sequential scheduling scheme reduces the average end-to-end delay by about 22%, 36%, 48%, and 55% respectively when compared to the random scheduling scheme.

• Journal of Communications and Networks
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• v.10 no.1
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• pp.28-37
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• 2008

In this paper, we investigate the problem of minimizing the average transmission power of users while guaranteeing the average delay constraints in time-varying uplink channels. We design a scheduler that selects a user for transmission and determines the transmission rate of the selected user based on the channel and backlog information of users. Since it requires prohibitively high computation complexity to determine an optimal scheduler for multi-user systems, we propose a low-complexity scheduling scheme that can achieve near-optimal performance. In this scheme, we reduce the complexity by decomposing the multiuser problem into multiple individual user problems. We arrange the probability of selecting each user such that it can be determined only by the information of the corresponding user and then optimize the transmission rate of each user independently. We solve the user problem by using a dynamic programming approach and analyze the upper and lower bounds of average transmission power and average delay, respectively. In addition, we investigate the effects of the user selection algorithm on the performance for different channel models. We show that a channel-adaptive user selection algorithm can improve the energy efficiency under uncorrelated channels but the gain is obtainable only for loose delay requirements in the case of correlated channels. Based on this, we propose a user selection algorithm that adapts itself to both the channel condition and the backlog level, which turns out to be energy-efficient over wide range of delay requirement regardless of the channel model.

• Journal of Communications and Networks
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• v.16 no.6
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• pp.656-666
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• 2014

In delay tolerant networks (DTNs), delay is inevitable; thus, making better use of buffer space to maximize the packet delivery rate is more important than delay reduction. In DTNs, epidemic routing is a well-known routing protocol. However, epidemic routing is very sensitive to buffer size. Once the buffer size in nodes is insufficient, the performance of epidemic routing will be drastically reduced. In this paper, we propose a buffer scheme to optimize the performance of epidemic routing on the basis of the Lagrangian and dual problem models. By using the proposed optimal buffer scheme, the packet delivery rate in epidemic routing is considerably improved. Our simulation results show that epidemic routing with the proposed optimal buffer scheme outperforms the original epidemic routing in terms of packet delivery rate and average end-to-end delay. It is worth noting that the improved epidemic routing needs much less buffer size compared to that of the original epidemic routing for ensuring the same packet delivery rate. In particular, even though the buffer size is very small (e.g., 50), the packet delivery rate in epidemic routing with the proposed optimal buffer scheme is still 95.8%, which can satisfy general communication demand.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.5
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• pp.1682-1701
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• 2015

In this paper, we propose an intergraded unified imperfect CSI model and investigate the joined effects of feedback delay and channel estimation errors (CEE) for two-hop relaying systems with transmit beamforming and relay selection. We derived closed-form expressions for important performance measures including the exact analysis and lower bounds of outage probability as well as error performance. The ergodic capacity is also included with closed-form results. Furthermore, diversity and coding gains based on the asymptotic analysis at high SNRs are also presented, which are simple and concise and provide new analytical insights into the corresponding power allocation scheme. The analysis indicates that delay effect results in the coding gain loss and the diversity order loss, while CEE will merely cause the coding gain loss. Numerical results verify the theoretical analysis and illustrate the system is more sensitive to transmit beamforming delay compared with relay selection delay and also verify the superiority of optimum power allocation. We further investigate the outage loss due to the CEE and feedback delays, which indicates that the effect of the CEE is more influential at low-to-medium SNR, and then it will hand over the dominate role to the feedback delay.

• Journal of KIISE:Information Networking
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• v.29 no.4
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• pp.397-404
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• 2002

We propose a heuristic distributed unicast routing algorithm for minimizing the total cost of the path in a point to point network with do]ay constraint. The algorithm maintains a delay vector and a cost vector about the network states and finds the path using this information. In this paper, we show that our algorithm always finds a delay-constrained path if such a path exists and has O(│E│) message complexity(│E│is the number of links in the network). Also, simulation results show that the proposed algorithm has better cost performance than other delay-constrained routing algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1261-1266
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• 2017

A random and systematic jitter suppressed delay locked loop (DLL)-based clock generator with a delay-time voltage variance converter (DVVC) and an averaging circuit (AC) is presented. The DVVC senses the delay variance of each delay stage and generates a voltage. The AC averages the output voltages of two consecutive DVVCs to suppress the systematic and random delay variance of each delay stage in the VCDL. The DVVC and AC averages the delay time of successive delay stages and equalizes the delay time of all delay stages. In addition, a capacitor with a switch working effectively as a negative feedback function is introduced to reduce the variation of the loop filter output voltage. Measurement results of the DLL-based clock generator fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process shows 13.4-ps rms jitter.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.6
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• pp.354-360
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• 2002

Delay estimation must be simple and efficient, since millions or more delay calculations may be required during a timing-driven placement stage. We have developed a new Modified Elmore delay estimation method, which is significantly more accurate than the original Elmore delay by considering resistance shielding effects, but has the same order of complexity with that of Elmore delay. Experimental results show that the suggested technique can significantly reduce the error in estimated delay, from 31.6 ~ 145.2% to 2.5 ~ 22.7%.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.701-707
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• 1987

This paper is concerned with an accurate delay time modling of the ED MOS logic gates and its application to the multiple delay logic simulator. The proposed delay model of the ED MOS logic gate takes account of the effects of not only the loading conditions but also the slope of the input waveform. Defining delay as the time spent by the current imbalance of the active inverter to charge and discharge the output load, with respect to physical reference levels, rise and fall model delay times are obtained in an explicit formulation, using optimally weighted imbalance currents at the end points of the voltage transition. A logic simulator which uses multiple rise/fall delays based on the model as decribed in the above has been developed. The new delay model and timing verification method are evaluated with repect to delay accuracy and execution time.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.5
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• pp.13-18
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• 1978

A delay switching PLL (DSPLL) is proposed for improvement of the frequency acquisition Performance (pull-in range) while keeping a narrow bandwidth LPF. It has, between the phase detector and the LPF, just a simple RC delay circuit, a switch and another phase detector controlling the switching time. For the common second order PLL, the pull-in capability of the DSPLL is analyzed approximately, without considering additive white noise effect, and verified experimentally. It is shown that the delay switching extends the pull-in range significantly, as much as a half of lock-range. At the phase tracking mode, the delay switching does not function, to make the DSPLL be a normal PLL.

• Journal of the Korea Society of Computer and Information
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• v.18 no.7
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• pp.79-84
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• 2013

In this paper, the method of multiple PS(pilot symbol) QAM channel compensation is suggested in order to analyze and improve occurring problems in case of delay waves in Frequency-Selective Rayleigh fading channels through Pilot Symbol Assisted Modulation(PSAM) which is a method predicting and compensating fading information, using Pilot Symbol in flat fading channels. This suggested method shows stable improvement in its performance even though it is effected by the level of delay on delay waves while the existing PSAM method has severe malfunction with a small amount of level of delay on delay waves regardless of signal-to-noise ratio(SNR).