• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.164-167
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• 2002

This paper presents the design of Rijndael crypto-processor with 128 bits, 192 bits and 256 bits key size. In October 2000 Rijndael cryptographic algorithm is selected as AES(Advanced Encryption Standard) by NIST(National Institute of Standards and Technology). Rijndael algorithm is strong in any known attacks. And it can be efficiently implemented in both hardware and software. We implement Rijndael algorithm in hardware, because hardware implementation gives more fast encryptioN/decryption speed and more physically secure. We implemented Rijndael algorithm for 128 bits, 192 bits and 256 bits key size with VHDL, synthesized with Synopsys, and simulated with ModelSim. This crypto-processor is implemented using on-the-fly key generation method and using lookup table for S-box/SI-box. And the order of Inverse Shift Row operation and Inverse Substitution operation is exchanged in decryption round operation of Rijndael algorithm. It brings about decrease of the total gate count. Crypto-processor implemented in these methods is applied to mobile systems and smart cards, because it has moderate gate count and high speed.

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.11
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• pp.1137-1143
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• 2009

This paper presents the FPGA implementation of efficient algorithms for approximating exponential function based on floating point format data. The Taylor-Maclaurin expansion as a conventional approximation method becomes inefficient since high order expansion is required for the large number to satisfy the approximation error. A format converter is designed to convert fixed data format to floating data format, and then the real number is separated into two fields, an integer field and an exponent field to separately perform mathematic operations. A new assembly command is designed and added to previously developed command set to refer the math table. To test the proposed algorithm, assembly program has been developed. The program is downloaded into the Altera DSP KIT W/STRATIX II EP2S180N Board. Performances of the proposed method are compared with those of the Taylor-Maclaurin expansion.

• Journal of the Korean Society of Industry Convergence
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• v.3 no.1
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• pp.9-15
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• 2000

This paper presents a implementation of digital motion control system for induction motor vector drives using the 16bit DSP TMS320F240. The DSP controller enable enhanced real time algorithm and cost-effective design of intelligent controllers for motors which can be yield enhanced operation, fewer system components, lower system cost, increased efficiency and high performance. The system presented are speed and current sensing, sine look-up table and generated SVPWM by fully integrated control software. The developed system in a implementation are shown a good speed response and motion control characteristic results, and high performance features in general purposed 2.2[kW] machine. The system can be adapted variform motor drive system.

• Journal of the Korean Operations Research and Management Science Society
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• v.12 no.1
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• pp.139-139
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• 1987

This study addresses basic requirements for mathematical programming software, discusses considerations in designing these software, implementation issues facing in these types of applications development, and shows some examples of codes being developed in the course. This type of projects requires long and ever-changing evolutionary phases. The experience is therefore, valuaable in suggesting some useful hints which may be salvaged for similar projects as well as providing reusable codes. In particular, scanning and parsing the free-format inputs, symbol table management, mixed-language programming, and data structures dealing with large sparse matrices are indispensable to many management science software development. Extensions to be made are also discussed.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.377-381
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• 1999

This paper presents a implementation of digital motion control system for induction motor vector drives using the 16bit DSP TMS320F240. The DSP controller enable enhanced real time algorithm and cost-effective design of intelligent controllers for induction motors which can be yield enhanced operation, fewer system components, lower system cost, increased efficiency and high performance. The system presented are speed and current sensing, sine look-up table and generated SVPWM by fully integrated control software. The developed system in a implementation are shown a good speed response characteristic results and high performance features. The system can be adapted variform motor drive system.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.349-350
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• 2008

Average throughput estimation of EV-DO forward link is implemented on the basis of the serving coverage area per sector instead of time consuming and complicated Monte Carlo simulation. For the implementation of this analysis function in cell planning tool, $CellTREK^{(R)}$, developed by KT, both SNR vs. DRC mapping table and receiver sensitivity are suggested as the satisfying criteria to be satisfied above each threshold level simultaneously.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.293-293
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• 2000

The SECS(SEMI Equipment Communications Standard) is a standard protocol for communication between equipments and a host in semiconductor processes. This paper proposes the implementation of the HSMS(High-speed SECS Message Services) as an interface for transmission of the SECS messages and SECS-II containing message contents defined as an SEMI standard. The HSMS driver is implemented as a type of the daemon program and several DLL files. The SECS-II composes of the SML(SECS Message Language) file defining the SECS messages, the SML translator being able to interpret and transform the SML, and the data index table being able to refer to SECS messages. We also define the shared parameter to exchange the HSMS header and SECS message between the HSMS and the SECS-II. Eventually, to show the effectiveness of the proposed drivers, we test the SECS communications between equipments and a host using the implemented communication programs.

• Proceedings of the KIEE Conference
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• 2001.04a
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• pp.281-284
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• 2001

This paper presents implementation of digitally speed sensorless control system for induction motor with a direct torque control(DTC) using 32bit DSP TMS320C31. The system are closed loop stator flux and torque observer for wide speed range that inputs are currents and voltages sensing of motor terminal, MRAS with rotor flux linkages for the speed turning signal, two hysteresis controllers, optimal switching look-up table and IGBT voltage source inverter. There are suggested a control algorithm and system, and given simulation and implementation results on the 2.2Kw general purposed induction motor.

• Journal of Institute of Control, Robotics and Systems
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• v.3 no.6
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• pp.588-593
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• 1997

This paper shows a design and implementation of throttle valve controller for engine dynamometer system using fuzzy logic. Recently, we demanded the excellent measuring equipment so as to improve engine performance. The throttle valve control for engine dynamometer system is a very particular part in the engine control. Since the structure of engine dynamometer system is very complicated and has nonlinear elements which are influenced by disturbance of vibration, heating, cooling, and energy loss so on. In this paper, fuzzy logic control application have been successful in throttle valve control problem for engine dynamometer system in which the conventional control had difficulties dealing with the system. In this study, we propose a method that the control strategy uses Fuzzy Look-up table and normalization and obtained the satisfying result from realized throttle valve controller for engine dynamometer system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.999-1007
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• 2002

In this paper, the operation of matched filter for searching initial synchronization in direct sequence spread spectrum receiver is studied. The implementation model of the matched filter by HDL (Hardware Description Language) is proposed. The model has an architecture based on parallelism and pipeline for fast processing, which includes circular buffer, multiplier, adder, and code look-up table. The performance of the model is analyzed and compared with the implementation by a conventional digital signal processor. It is implemented on a FPGA (Field Programmable Gate Array) and its operation is validated in a timing simulation result.