• Journal of Power Electronics
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• v.16 no.2
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• pp.473-479
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• 2016

In this paper, the PSC PWM method is chosen as the optimal modulation method for a 20MW VSC HVDC, with consideration of the harmonic distortion of the output voltage, the switching frequency, and the control implementation difficulty. In addition, a new PSC PWM method is proposed in order to achieve an easy application and to solve the redundant control problems encountered in the previous PSC PWM method. To verify the proposed PSC PWM method, PSCAD/EMTDC simulations for an 11-level MMC RTDS HILS test and an 11-level MMC prototype converter test were performed. As can be seen from the results of these tests, the proposed PSC PWM method shows good results in an 11-level MMC with redundant sub-modules.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.129-130
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• 2010

For the high power demand and N+1 redundancy, this paper presents the digital load share (LS) controller design and the implementation of paralleled phase-shifted full-bridge converters (PSFBC) used in distributed power systems. By adopting the digital control strategy, separately used ICs for PSFBC and LS control functions in analog systems can be merged into a cost-effective digital controller. To compensate and stabilize both PSFBC and LS loops with the direct digital design approaches, small-signal model of the system is derived in discrete-time domain. The steady-state and dynamic load sharing performances are also investigated. Experimental results from two 1.2 kW paralleled PSFBC modules are shown to verify the proposed work.

• Journal of Power Electronics
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• v.11 no.1
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• pp.21-27
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• 2011

In this paper, an approach to reduce common-mode voltage (CMV) at the output of multilevel inverters using a phase opposition disposed (POD) sinusoidal pulse width modulation (SPWM) technique is proposed. The SPWM technique does not require computations therefore, this technique is easy to implement on-line in digital controllers. A good tradeoff between the quality of the output voltage and the magnitude of the CMV is achieved in this paper. This paper realizes the implementation of a POD-SPWM technique to reduce CMV using a five-level diode clamped inverter for a three phase induction motor. Experimental and simulation results demonstrate the feasibility of the proposed technique.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1278-1287
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• 2017

Inverters are widely used in distributed power generation and other applications. However, their lack of inertia and variable impedance may cause system instability and power transfer inaccuracy. This paper proposes a control scheme for a single phase voltage-controlled inverter with some grid-friendly characteristics. The proposed control algorithm enables the inverter to function as a voltage source with an inner output impedance in both the islanded and grid-connected modes. Virtual inertia and rotor equations are embedded in the PLL part. Thus, the frequency stability can remain. The inner output impedance can be adjusted freely, which helps to accurately decouple and transmit the output active and reactive power. The proposed inverter operates like a traditional synchronous generator. Simulations and experiments are designed and carried out to verify the proposed control strategy.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.05a
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• pp.110-110
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• 2004

하나 또는 다수개의 압전액츄에이터(piezoelectric actuator)로 구성된 시스템에서 구동 효율을 높이는데 직접적인 영향을 미치는 고정밀과 빠른 응답 특성을 구현(implementation)하기 위하여, 입력전압에 대하여 출력전압이 선형적으로 추종하고 주파수 가변(variable)이 독립적이며 순차적으로 제어가 가능한 위상가변(phase shifting)형 압전액츄에이터 구동장치의 설계가 필요하다. 구동신호론 증폭하고 가변하는 고전압 증폭 구동장치는 압전액츄에이터 구동에 직접 영향을 주게 되므로, 이의 특성인 고주파에서의 위상지연 보상, 높은 회전비(slew rate)로 고전압에서 정현파의 찌그럼짐을 방지, 전압이득의 가변 및 안정화, 입력 및 출력 임피던스의 개선과 주파스 대역폭(band width)의 확장 등은 매우 중요하다.(중략)

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.2
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• pp.219-225
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• 1998

A voltage controlled oscillator for the local oscillator in 380 MHz TRS handset is designed and fabricated. To improve the phase noise characteristics, the NEC's 2SC4226 transistor with NF=1.2 at 1 GHz and Toshiba's 1SV229 varactor diode with Q=70 are used. And an inductor of VCO is realized by microstrip line. At the bias condition of 5 V and 10 mA, the output power and phase noise in the operating frequency range of 357∼387 MHz are above 3.7 dBm and 111 dBc/Hz at 12.5KHz offset from the carrier, respectively. And FM sensitivity deviation are within ±0.4 KHz. This VCO is well suited for TRS handset.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.1014-1015
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• 2006

In this paper, a new single phase voltage sag/swell compensator using direct power conversion is introduced. A new compensator consists of input/output filter, series transformer and direct at-ac converter, which is a single-phase back-to-back PWM converter without dc-link capacitors. Advantages of the proposed compensator include: simple power circuit by eliminating dc-link electrolytic capacitors and thereby, improved reliability and increased life time of the entire compensator; simple PWM strategy to compensate voltage sag/swell at the same time and reduced switching losses in the ac-ac converter. Further, the proposed scheme is able to adopt simple switch commutation method without requiring complex four-step commutation method commonly required in the direct power conversion. Simulation results are shown to demonstrate the advantages of the new compensator and PWM strategy.

• Proceedings of the KOSOMBE Conference
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• v.1995 no.05
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• pp.167-170
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• 1995

A quadrature-channel MODEM using amplitude modulation was constructed. To test the MODEM, 6.4 MHz sinusoidal wave 1 KHz triangular wave were modulated, then the modulated signal was fed into the demodulator, to reconstruct the triangular wave.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1984-1987
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• 2002

This paper describes the design and implementation of a single-chip digitally synthesized 0-35MHz agile function generator. The chip comprises an integrated direct digital synthesizer (DDS) with a 10-bit on- chip digital-to-analog converter (DAC) using an n-well single-poly triple-metal 0.5-$\mu\textrm{m}$ CMOS technology. The main features of the chip include maximum clock frequency of 100 MHz at 3.3-V supply voltage, 32-bit frequency tuning word resolution, 12-bit phase tuning word resolution, and an on-chip 10-bit DAC. The chip provides sinusoidal, ramp, saw-tooth, and random waveforms with phase and frequency modulation, and power-down function. At 100-MHz clock frequency, the chip covers a bandwidth from dc to 35 MHz in 0.0233-Hz frequency steps with 190-ns frequency switching speed. The complete chip occupies 12-mm$^2$die area and dissipates 0.4 W at 100-MHz clock frequency.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.1
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• pp.85-92
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• 2012

In this paper, a 300[W] class boost type single-phase inverter system which can compensate voltage sag on source side is designed and implemented. This system is a two-stage conversion system composed of a boost converter and a PWM inverter. If the voltage sag has appeared at the point of common coupling, the boost converter would be operated to compensate it. The boost converter and the inverter were constructed on single smart power module(SPM) to implement low cost system. The system is designed for that the THD of output voltage is below 5[%]. Finally, the validity of the design for the inverter system is verified by both simulations and experiments.