• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.3
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• pp.555-562
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• 2007

In order to display Bayer input stream received from CMOS image sensor to the display device, image signal processing must be performed. That is, the hardware performing the image signal processing for Bayer data is called ISP(Image Signal Processor). We can see real image through ISP processing. ISP executes functionalities for gamma correction, interpolation, color space conversion, image effect, image scale, AWB, AE and AF. In this paper, we obtained the optimum algorithm through software verification of ISP module for CMOS camera image sensor and described using VHDL and verified in ModelSim6.0a simulator. Also we downloaded into Xilinx XCV-1000e for the designed ISP module and completed the board level verification using PCI interface.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1737-1744
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• 2010

The Image sensor needs various image processing to improve image quality. ISP(Image Signal Processor) performs various image processing. Conventional vision cameras have own software ISP functions and perform in PC instead of using commercial ISP chips. However these methods have problems such as large computation for image processing. In this paper, we proposed ISP that significantly reduced chip area by efficient sharing of hardware and software. Large operation blocks are designed to hardware for high performances, and we used hardware simultaneously with software considering the size of the hardware. The implemented ISP can process VGA(640*4800) images and has 91450 gate sizes in 0.35um process.

• Journal of IKEEE
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• v.20 no.1
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• pp.89-93
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• 2016

In this paper, we proposed SIMT based Image Signal Processor which can apply various image preprocessing algorithms and allow parallel processing of application programs such as image recognition. Conventional ISP has the hard-wired image enhancement algorithm of which the processing speed is fast, but there was difficult to optimize performance depending on various image processing algorithms. The proposed ISP improved the processing time applying SIMT architecture and processed a variety of image processing algorithms as an instruction based processor. We used Xilinx Virtex-7 board and the processing time compared to cell multicore processor, ARM Cortex-A9, ARM Cortex-A15 was reduced by about 71 percent, 63 percent and 33 percent, respectively.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.103-111
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• 2007

In this paper, we propose a VLSI architecture of hardware optimized high quality image signal processor for a Single-chip CMOS Image Sensor(CIS). The Single-chip CIS is usually used for mobile applications, so it has to be implemented as small as possible while maintaining the image quality. Several image processing algorithms are used in ISP to improve captured image quality. Among the several image processing blocks, demosaicing and image filter are the core blocks in ISP. These blocks need line memories, but the number of line memories is limited in a low cost Single-chip CIS. In our design, high quality edge-adaptive and cross channel correlation considered demosaicing algorithm is adopted. To minimize the number of required line memories for image filter, we share the line memories using the characteristics of demosaicing algorithm which consider the cross correlation. Based on the proposed method, we can achieve both high quality and low hardware complexity with a small number of line memories. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 37K, and seven and half line memories are used.

• Journal of the Institute of Convergence Signal Processing
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• v.17 no.1
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• pp.26-31
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• 2016

In this paper, we propose an image quality evaluation system for compact camera module and assess the effect of optical performance improvement for proposed anti-halation disk in small lens. We develop a image quality evaluation system for quality estimation of camera module image. And we also develop a program to control register in image signal processor. Finally the resolution, brightness, and color reproduction performances were evaluated image quality comparison between conventional and proposed camera module using developed quality evaluation system and ISP register control program.

• Proceedings of the Korea Information Processing Society Conference
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• 2024.05a
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• pp.18-19
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• 2024

High Dynamic Range 는 디지털 카메라에 내장된 영상 보정 장치인 Image Signal Processor 의 주요 기능 중 하나로서, 영상의 밝고 어두운 정도의 범위를 넓혀, 피사체가 더 또렷하게 보이도록 한다. 초당 수십 프레임을 촬영하는 경우, 실시간 보정처리를 위해 ISP 에 사용되는 기능 및 알고리즘은 신속성과 효율성이 요구된다. 본 연구는 ISP 에 적합한 HDR 알고리즘을 선정을 목표로 하여, Histogram Equalization 과 Contrast Limited Adaptive Histogram Equalization 을 소개한다. 이어 해당 알고리즘들을 컴퓨터 프로그래밍으로 구현, CMOS 이미지 센서를 통해 추출한 raw image 를 보정하여 각 알고리즘의 성능을 검토하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.1784-1787
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• 2010

General Purpose Graphic Processing Unit (GPGPU) computing is a technique that utilizes the high-performance many-core processors of high-end graphic cards for general-purpose computations such as 3D graphics, video/image processing, computer vision, scientific computing, HPC and many more. GPGPUs offer a vast amount of raw computing power, but programming is extremely challenging because of hardware idiosyncrasies. The open computing language (OpenCL) has been proposed as a vendor-independent GPGPU programming interface. OpenCL is very close to the hardware and thus does little to increase GPGPU programmability. In this paper we present how a set of digital camera image signal processing (ISP) filters can be realized efficiently on GPGPUs using OpenCL. Although we found ISP filters to be memory-bound computations, our GPGPU implementations achieve speedups of up to a factor of 64.8 over their sequential counterparts. On GPGPUs, our proposed optimizations achieved speedups between 145% and 275% over their baseline GPGPU implementations. Our experiments have been conducted on a Geforce GTX 275; because of OpenCL we expect our optimizations to be applicable to other architectures as well.

• Proceedings of the Korea Information Processing Society Conference
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• 2024.05a
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• pp.860-861
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• 2024

본 연구는 ISP(Image Signal Processing) 모듈에 적용 가능한 HDR(High Dynamic Range)을 위한 Log Histogram Equalization 기법을 제안한다. 기존의 HDR 기술은 다양한 노출로 찍은 사진들을 합쳐서 한 장의 사진에서 더 넓은 동적 범위를 담아내는 방식에 집중해 왔다. 이 연구에서는 단일 노출 이미지에서도 향상된 HDR 을 구현하기 위해, 로그 함수를 이용한 히스토그램 평준화 방법을 탐구한다. 이 기법은 로그 함수의 특성을 활용하여 이미지의 대비를 증가시킨다. 또한, 룩업 테이블과 선형 근사를 도입하여 연산량을 줄이고, ISP 모듈 내에서의 실시간 처리 가능성을 높인다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.109-112
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• 2007

Definition-Enhancement of the digitalized image has been being made researches continuously due to application a camera to a mobile-apparatus and the advent of a digital camera. In particular, the inputted image from a sensor goes through the process of ISP(Image Signal Process) prior to output as a visual image. The high-frequency components are offset by LPF(Low Pass Filter) that eliminates the noise of high spatial-frequency at the moment. In this paper, we propose an algorithm that outputs more vivid image by using adaptive-HPF(High Pass Filter) that has apt coefficients for diverse conditions of an image edge, nevertheless we do not employ any Edge-Detection algorithm to enhance a blurred image.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.503-506
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• 2015

In accordance with IoT(Internet of Things) commercialization, the need to design SoC-based hardware platform with wireless communication is increasing. This paper therefor proposes an SoC platform architecture with Smart Frame System inter-communicating between devices. Wireless communication functions and high-performance real-time image processing hardware structure was applied to existing digital photo frame. We developed a smart phone application to control the smart frame through Bluetooth communication. The SoC platform hardware consists of CIS controller, Memory controller, ISP(Image Signal Processing) module for image scaling, Bluetooth Interface for inter-communicating between devices, VGA/TFT-LCD controller for displaying video. The Smart Frame System to support the IoT services was implemented and verified using HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA. The operating frequency is 54MHz.