• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.40 no.2
• /
• pp.17-25
• /
• 2003

In this paper, a processor architecture is proposed based on the state space implementation technique for real time processing of 2-D discrete wavelet transform(DWT). It conducts 2-D DWT operations in consideration of row and column direction simultaneously, thus can reduce latency due to memory access for storing intermediate results. It is a VLSI architecture suitable for real time processing. The proposed architecture includes only four multipliers and four adders, and NK-N internal memory storage, where K denotes the length of filter. It has a small hardware complexity. Therefore it is very suitable architecture for real time, embedded applications such as web camera server. Since the processor is easily extended to array structure, it can be applied to various image processing applications.

• The Journal of the Korea Contents Association
• /
• v.13 no.4
• /
• pp.44-52
• /
• 2013

The SIFT algorithm is being actively researched for various image processing applications including video surveillance and autonomous vehicle navigation. The computation of sin/cos function is the most cost part needed in whole computational complexity and time for SIFT descriptor. In this paper, we implement a hardware to sin/cos function of descriptor on sift feature detection algorithm. The proposed Sin/Cosine processor is coded in Verilog and synthesized and simulated using Xilinx ISE 9.2i. The processor is mapped onto the device Spartan 2E (XC2S200E-PQ208-6). It consumes 149 slices, 233 LUTs and attains a maximum operation frequency of 60.01 MHz. As compared with the software realization, our FPGA circuit can achieve the speed improvement by 40 times in average.

• 전자공학회논문지 IE
• /
• v.47 no.3
• /
• pp.1-6
• /
• 2010

In this paper, it is designed a processor using embedded system so that moving picture can be expressed on LED electric sign board which has been expressed a simple message only like as a character or graphic. It has been fabricated a moving picture LED electric sign board which is composed to a video processor and LED display panel, in order to be able to express a digital moving picture of 24 bits that is transmitted from embedded system. It includes gamma adjustment, brightness, color contrast control, a schedule function, expression image conversion by the Internet and memory device. Also, an application program based Windows CE is designed so that a character, graphic, and moving picture can be expressed on a small LED electric sign board.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.2
• /
• pp.1107-1111
• /
• 2005

The DVR system realization with watermarking and MPEG-4 for real time processing speed improvement is presented in this paper. For the real time processing the system is used the DSP processor, Quick DMA for data transmission, watermarking for security and MPEG-4 compression for facility. The algorithms are that the operational structure has the internal memory of processor, and the optimal realization is suitable to form the DSP processor structure r processed for the iterative operations. The experimental result shows the real time processing is improved 12% over for the D1 image in comparison with the other system.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2009.01a
• /
• pp.751-754
• /
• 2009

This paper deals with the Cell-based distributed processing for generating free viewpoint images by merging multiple differently focused images. We previously proposed the method of generating free viewpoint images without any depth estimation. However, it is not so easy to realize real-time image reconstruction based on our previous method. In this paper, we discuss the method to reduce the processing time by dimension reduction for image filtering and Cell-based distributed processing. Especially, the method of high-speed image reconstruction by the Cell processor on SONY PLAYSTATION3(PS3) is described in detail. We show some experimental results by using real images and we discuss the possibility of real-time free viewpoint image reconstruction.

• The KIPS Transactions:PartA
• /
• v.18A no.3
• /
• pp.99-108
• /
• 2011

Processor technology is currently continued to parallel processing techniques, not by only increasing clock frequency of a single processor due to the high technology cost and power consumption. In this paper, a SIMD (Single Instruction Multiple Data) based parallel processor is introduced that efficiently processes massive data inherent in multimedia. In addition, this paper proposes pixel subword parallel processing instructions for the SIMD parallel processor architecture that efficiently operate on the image and video pixels. The proposed pixel subword parallel processing instructions store and process four 8-bit pixels on the partitioned four 12-bit registers in a 48-bit datapath architecture. This solves the overflow problem inherent in existing multimedia extensions and reduces the use of many packing/unpacking instructions. Experimental results using the same SIMD-based parallel processor architecture indicate that the proposed pixel subword parallel processing instructions achieve a speedup of $2.3{\times}$ over the baseline SIMD array performance. This is in contrast to MMX-type instructions (a representative Intel multimedia extension), which achieve a speedup of only $1.4{\times}$ over the same baseline SIMD array performance. In addition, the proposed instructions achieve $2.5{\times}$ better energy efficiency than the baseline program, while MMX-type instructions achieve only $1.8{\times}$ better energy efficiency than the baseline program.

• Journal of Institute of Control, Robotics and Systems
• /
• v.21 no.4
• /
• pp.309-314
• /
• 2015

In this study, an embedded ranging system based on a laser structured light image is developed. The distance measurement by the structured light image processing has efficient computation because the burdensome correspondence problem is avoidable. In order to achieve robustness against environmental illumination noise and real-time laser structured light image processing, a bandpass optical filter is adopted in this study. The proposed ranging system has an embedded image processor performing the whole image processing and distance measurement, and so reduces the computational burden in the main control system. A system calibration algorithm is presented to compensate for the lens distortion.

• Proceedings of the Korean Society for Emotion and Sensibility Conference
• /
• 2000.04a
• /
• pp.330-336
• /
• 2000

A color is the most important of all factors that have influence on interior spaces, and plays an visually and psychologically important role in making interior environment. Thus, the aim of this study is to propose predictable color models by image types specially for color design in living room.This study was composed of three steps, and was carried out as follows.1) The evaluation experiment was carried out by color simulation using Color Image Processor. 2) Image types were extracted by factor analysis. 3) The characteristics of colors by image types were analysed by the multi regression and as a result the predictable color models by image types was determined.

• Journal of Biomedical Engineering Research
• /
• v.8 no.2
• /
• pp.117-117
• /
• 1987

The medical image processing system is intended for a diverse set of users in the medical Imaging Parts. This system consists of a 640 Kbyte IBM-PC/AT with 30 Mbyte hard disk, special purpose image processor with video input devices and display monitor. Image may be recorded and processed in real time at sampling rate up to 10 MHz. This system provides a wide range of image enhancement processing facilities via a menu-driven software packages. These facilities include point by point processing, image averaging, convolution filter and subtraction.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.36S no.11
• /
• pp.34-43
• /
• 1999

A high-speed image processor (HIP) is implemented for a high-speed multi-function peripheral. HIP has a binarization architecture with unified data path. It has the pixel-by-pixel pipelined processing to minimize size of the external memory. It performs pre-processing such as shading correction, automatic gain control (AGC), and gamma correction, and also drives external CCD or CIS modules. The pre-processed data can be enlarged or reduced. Various binarizatin algorithms can be processed in the unified archiecture. The embedded binarization algorithms are simple thresholding, high pass filtering, dithering, error diffusion, and thershold modulated error diffusion. These binarization algorithms are unified based on th threshold modulated error diffusion. The data path is designed to share the common functional block of the binarization algorithms. The complexity of the controls and the gate counts is greatly reduced with this novel architecture.