The Journal of the Korea Contents Association (한국콘텐츠학회논문지)

The Korea Contents Association (한국콘텐츠학회)
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Implementation of sin/cos Processor for Descriptor on SIFT

SIFT의 descriptor를 위한 sin/cos 프로세서의 구현

  • Received : 2013.03.13
  • Accepted : 2013.04.02
  • Published : 2013.04.28
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Abstract

The SIFT algorithm is being actively researched for various image processing applications including video surveillance and autonomous vehicle navigation. The computation of sin/cos function is the most cost part needed in whole computational complexity and time for SIFT descriptor. In this paper, we implement a hardware to sin/cos function of descriptor on sift feature detection algorithm. The proposed Sin/Cosine processor is coded in Verilog and synthesized and simulated using Xilinx ISE 9.2i. The processor is mapped onto the device Spartan 2E (XC2S200E-PQ208-6). It consumes 149 slices, 233 LUTs and attains a maximum operation frequency of 60.01 MHz. As compared with the software realization, our FPGA circuit can achieve the speed improvement by 40 times in average.

SIFT(Scale Invariant Feature Transform) 알고리즘은 현재 비디오 감시카메라, 자율 주행시스템 등과 같은 영상 시스템에서 많이 사용되고 있다. SIFT 알고리즘에서 연산량과 연산시간이 가장 많이 필요한 부분이 descriptor의 sin/cos 함수를 연산하는 부분이다. 그러므로 본 논문에서는 SIFT 알고리즘에 사용되는 descriptor를 위한 sin/cos 함수를 하드웨어로 구현하였다. Verilog-HDL 언어를 사용하여 FPGA로 구현하고 그 성능을 분석한다. Xilinx Spartan 2E(XC2S200E-PQ208-6) 를 사용하여 구현하였을때, 149 Slices에 233 LUTs가 소모되었으며, 최대 주파수는 60.01MHz로 동작하였다. 또한 descriptor에 적용하여 소프트웨어와 비교 하였을 때 40배 정도의 빠른 성능 향상을 얻었다.

Keywords

References

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