• Proceedings of the Korea Information Processing Society Conference
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• 2014.04a
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• pp.31-32
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• 2014

다중의 명령어를 동시에 수행할 수 있는 멀티코어 시스템의 특성으로 하나의 시스템 내에서 태스크를 수행하면서 외부 이벤트의 발생에 의한 인터럽트를 동시에 처리할 수 있다. 각 태스크가 처리되어야 하는 시간에 제약성을 갖는 실시간 시스템에서는 스케줄러에 의해 CPU 코어에서의 수행이 제어되어야한다. 본 논문에서는 최적이라고 알려진 Pfair 멀티코어 스케줄러의 각 코어별 유휴시간을 정량적으로 평가함으로써 인터럽트 처리의 지연시간을 분석한다.

• Journal of Industrial Convergence
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• v.5 no.2
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• pp.21-32
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• 2007

This paper deals with the sequencing problem in the operation of the manufacturing systems with the constraint of buffer capacity. Some of studies for this theme have been progressed for several years. And then most of them considered only one objective, such as maximum lateness, machine utilization, makespan, mean flowtime and so on. This study deal with two objectives of the delivery for customers and the idle time of machines for producers. For the decision of sequence, the utility function is used. The developed heuristic algorithm presents a good solution. Through a numerical example, the procedures of the job sequencing is explained.

• Journal of Korean Institute of Industrial Engineers
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• v.32 no.4
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• pp.369-372
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• 2006

Suppose that a customer arrives at the GI/M/1/K queueing system when there are customers in the system, $n,m{\geq}0,\;n+m{\leq}K$. Sooner or later, the number of customers in the system will reach . In this paper, we present the Laplace transform of the remaining interarrival time upon reaching level, for the first time, since a customer arrived when there are customers in the system.

• Journal of the Korean Operations Research and Management Science Society
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• v.19 no.2
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• pp.217-228
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• 1994

This paper presents a new integer formulation (Type III ALB) for a single model assembly line balancing problem. The objective of the formulation is to minimize the total idle time, which is defined as the product of the number of work stations and the cycle times minus the total work content. This formulation considers currently existing Type I (minimizing the number of work stations for a given cycle time) and type II (minimizing the cycle time for a given number of work stations) formulations as its special cases and provides the global minimum solutions of the cycle time and the number of work stations. This information would be of great value to line designers involved in designing new assembly lines and rebalancing old lines under flexible conditions. Solution methods based on combination of Type I and Type II approaches are also suggested and compared.

• Industrial Engineering and Management Systems
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• v.6 no.2
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• pp.106-118
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• 2007

This paper present a new optimization model to generate aggregate production planning by considering electric cost. The new Time Of Switching (TOS) electric type is introduced by switching over Time Of Day (TOD) and Time Of Use (TOU) electric types to minimize the electric cost. The fuzzy demand and Dynamic inventory tracking with multiple plant capacity are modeled to cover the uncertain demand of customer. The constraint for minimum hour limitation of plant running per one start up event is introduced to minimize plants idle time. Furthermore; the Optimal Weight Moving Average Factor for customer demand forecasting is introduced by monthly factors to reduce forecasting error. Application is illustrated for multiple cement mill plants. The mathematical model was formulated in spreadsheet format. Then the spreadsheet-solver technique was used as a tool to solve the model. A simulation running on part of the system in a test for six months shows the optimal solution could save 60% of the actual cost.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.257-263
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• 2002

Test scheduling of SoC becomes more important because it is one of the prime methods to minimize the testing time under limited power consumption of SoCs. In this paper, a heuristic algorithm, in which test resources are selected for groups and arranged based on the size of product of power dissipation and test time together with total power consumption in core-based SoCs is proposed. We select test resource groups which has maximum power consumption but does not exceed the constrained power consumption and make the testing time slot of resources in the test resource group to be aligned at the initial position to minimize the idle test time of test resources.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06a
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• pp.217-219
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• 2006

내장형 시스템에서 많이 채택되고 있는 자바 가상 머신의 성능을 향상시키기 위해 interpreter. just-in-time 컴파일러 (JITC), ahead-of-time 컴파일러 (AOTC) 세가지 방식을 모두 지원하는 자바 가상 머신을 설계하고 구현하였다. 특히 이런 환경을 지원하기 위한 효율적인 JITC와 시스템의 idle 시간에 JITC모듈을 활용하기 위한 client-AOTC의 설계와 구현에 대해 살펴보고 현재까지의 실험 결과를 보고한다.

• Journal of the Korea Society of Computer and Information
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• v.5 no.2
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• pp.121-129
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• 2000

The fuzzy-based SAM algorithm is proposed in this thesis to reduce the idle time. to recover call truncation fast when it is handed off and to last frequency acquisition in the mobile communications. It has additive and adaptive elements. Its weight values are generated not by feedback but by input conversion values. The initial expectation value is defined and forwardㆍbackward searching is executed 4o produce the expectation value of one chip. The fuzzy-based SAM algorithm is applied to the demodulator in CDMA system, and the synchronization time is measured. Synchronization time of PN code is 1.678$\mu\textrm{s}$ by SAM algorithm. It is 993 times faster than time of the conventional systems, 1.667$\mu\textrm{s}$.

• International journal of advanced smart convergence
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• v.7 no.3
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• pp.92-100
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• 2018

In this paper, we propose a fault-tolerant scheduling scheme with energy efficiency for real-time periodic tasks on DVFS-enabled multicore processors. The scheme provides the tolerance of a permanent fault with the primary-backup task model. Also the scheme reduces the energy consumption of real-time tasks with the fully overlapped execution between each primary task and its backup task, whereas most of previous methods tried to minimize the overlapped execution between the two tasks. In order to the leakage energy loss of idle cores, the scheme activates a part of available cores with rarely used cores powered off. Evaluation results show that the proposed scheme saves up to 82% energy consumption of the previous method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.61-71
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• 2007

The instruction level parallelism, which has been used to improve the performance of processors, expose its limit. The change of a control flow by a branch miss prediction is one of the obstacles that restrict the instruction level parallelism. The single chip multiprocessors have been developed to utilize the thread level parallelism. However, we could not use the maximum performance of the single chip multiprocessor in case of executing the coded programs without considering the multi-thread. In order to overcome the two performance degradation factors, in this paper, we suggest the concurrent branch execution method that applies to the multi-path execution method at a single chip multiprocessor. We executes all two flows of the conditional branch using the idle core processor. Through this, we can improve the processor's efficiency with blocking the control flow termination by the branch instruction and reducing the idle time. We analyze the effects of concurrent branch execution proposed in this paper through the simulation. As a result of that, concurrent branch execution reduces about 20% of idle time and improves the maximum 10% of the branch prediction accuracy. We show that our scheme improves the overall performance of maximum 39% compared to the normal single chip multiprocessor and maximum 27% compared to the superscalar processor.