• The Journal of the Acoustical Society of Korea
• /
• v.26 no.5
• /
• pp.214-219
• /
• 2007

This paper proposes a new IFFT(Inverse Fast Fourier Transform) algorithm, which is proper for IMDCT(Inverse Modified Discrete Cosine Transform) of MPEG-2 AAC(Advanced Audio Coding) decoder. The $2^n$(N-point) type IMDCT is the most powerful among many IMDCT algorithms, however it includes IFFT that requires many calculation cycles. The IFFT used in $2^n$(N-point) type IMDCT employ the bit-reverse data arrangement of inputs and N/4-point complex IFFT to reduce the calculation cycles. We devised a new data arrangement method of IFFT input and $N/4^{n+1}$-type IFFT and thus we can reduce multiplication cycles, addition cycles, and ROM size.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.12C
• /
• pp.1167-1176
• /
• 2009

In This Paper, we introduce an efficient IFFT design technique named for transmitter of OFDM (Orthogonal Frequency Division Multiplexing) system. In OFDM system, a cyclic prefix is inserted in forepart of OFDM symbol to prevent ICI(Inter-channel Interference) and ISI (Inter-symbol Interference). Attaching cyclic prefix causes delay in storing and copying IFFT result. The proposed IFFT removes this delay because its output is cyclic shifted by the length of cyclic prefix. So we can make a complete OFDM symbol by just copying the forepart of IFFT output to the end. In many cases, the length of cyclic prefix is 1/2n of FFT size, and this IFFT does not require additional hardware complexity and it does not cause any performance degradation.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.5
• /
• pp.66-73
• /
• 2015

IFFT is one of the key components in OFDM-based communication systems. In this paper, we propose a new memory efficient IFFT design method for OFDM-based communication systems, based on a mapping of three IFFT input signals which consist of modulated data, pilot and null signals. The proposed method focuses on reducing the memory size in the bit-reversal block which requires the largest number of memory cells in IFFT architectures. To reduce the memory size, we propose a selection mapping method based on decimation-in-time (DIT) algorithm. It is shown that the proposed method achieves a memory reduction of about 50% compared to conventional methods.

• ETRI Journal
• /
• v.44 no.3
• /
• pp.379-388
• /
• 2022

This study proposes a novel low-complexity algorithm for computing inverse fast Fourier transform (IFFT)/fast Fourier transform (FFT) operations in binary phase shift keying-modulated orthogonal frequency division multiplexing (OFDM) communication systems without requiring any twiddle factor multiplications. The peak-to-average power ratio (PAPR) reduction capacity of an efficient PAPR reduction technique, that is, H-SLM method, is evaluated using the proposed IFFT algorithm without any complex multiplications, and the impact of oversampling factor for the accurate calculation of PAPR is analyzed. The power spectral density of an OFDM signal generated using the proposed multiplierless IFFT algorithm is also examined. Moreover, the bit-error-rate performance of the H-SLM technique with the proposed IFFT/FFT algorithm is compared with the classical methods. Simulation results show that the proposed IFFT/FFT algorithm used in the H-SLM method requires no complex multiplications, thereby minimizing power consumption as well as the area of IFFT/FFT processors used in OFDM communication systems.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.11
• /
• pp.11-18
• /
• 2007

FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems such as WiBro, DAB and UWB systems. Most of the researches on the implementation of FFT processors have focused on reducing the complexities of multipliers, memory and control circuits. In this paper, to reduce the memory size required for IFFT(Inverse Fast Fourier Transform), we propose a new IFFT design method based on a mapping method. By simulations, it is shown that the reposed IFFT design method achieves more than 60% area reduction and much SQNR(Signal-to-Quantization-Noise Ratio) gain compared with previous IFFT circuits.

• Proceedings of the IEEK Conference
• /
• 2002.06a
• /
• pp.5-8
• /
• 2002

In this paper, we are designed and verified a FFT/IFFT processor that is possible from the wireless LAN environment which is adopted international standard of the IEEE802.11a. The proposed architecture of the FFT/IFFT has Radix-2 64point SDF(single-path delay feedback) Pipeline technique and DIF(Decimation in Frequenct) structure. The FFT/IFFT processor has each 8 bit complex input-output and 6 bit Twiddle factor. we used Max-PlusII for simulation and can see that processor is properly operated

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.12
• /
• pp.87-94
• /
• 2003

In this paper, we propose an IFFT/FFT design method to minimize quantization error in IEEE 802.11a WLAN. In the proposed algorithm, the twiddle coefficient of IFFT/FFT processor is manipulated by the statistics distribution of the input data at each stage. We applies this algorithm to radix-2/$^2$ SDF architecture. Both IFFT and FFT processor shares the circuit blocks cause to the symmetric architecture. The maximum quantization error with the 10 bits length of the input and output data is 0.0021 in IFFT and FFT that has a self-loop structure with the proposed method. As a result, the proposed architecture saves 3bits for the data to keep the same resolution compared with the conventional method.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.13 no.1
• /
• pp.42-47
• /
• 2020

In OFDM-based very high-speed communication systems, FFT/IFFT processor should have several properties of low-area and low-power consumption as well as high throughput and low processing latency. Thus, radix-2k MDF (multipath delay feedback) architectures by adopting pipeline and parallel processing are suitable. In MDF architecture, the feedback memory which increases in proportion to the input signal word-length has a large area and power consumption. This paper presents a feedback memory size reduction method of radix-22 MDF IFFT processor for OFDM applications. The proposed method focuses on reducing the feedback memory size in the first two stages of MDF architectures since the first two stages occupy about 75% of the total feedback memory. In OFDM transmissions, IFFT input signals are composed of modulated data and pilot, null signals. In order to reduce the IFFT input word-length, the integer mapping which generates mapped data composed of two signed integer corresponding to modulated data and pilot/null signals is proposed. By simulation, it is shown that the proposed method has achieved a feedback memory reduction up to 39% compared to conventional approach.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.3
• /
• pp.570-576
• /
• 2004

In this paper, we design the IFFT/FFT (Inverse fast Fourier Transform/Fast Fourier Transform) modules for IEEE 802.11a-1999, which is a standard of the High-speed Wireless LAN using the OFDM (Orthogonal Frequency Division Multiplexing). The designed IFFT/FFT is the 64-point FFT to be compatible with IEEE 802.11a and the pipelined architecture which needs neither serial-to-parallel nor parallel-to-serial converter. We compare four types of IFFT/FFT modules for the hardware complexity and operation : R22SDF (Radix-2 Single-path Delay feedback), the R2SDF (Radix-2 Single-path Delay feedback), R2SDF (Radix-4 Single-path Delay Feedback), and R4SDC (Radix-4 Single-path Delay Commutator). In order to minimize the error, we design the IFFT/FFT module to operate with additional decimal parts after butterfly operation. In case of the R22SDF, the IFFT/FFT module has 44,747 gate counts excluding RAMs and the minimized error rate as compared with other types. And we know that the R22SDF has a small hardware structure as compared with other types.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.46 no.1
• /
• pp.71-78
• /
• 2009

Sound source localization systems in service robot applications estimate the direction of a human voice. Time delay information obtained from a few separate microphones is widely used for the estimation of the sound direction. Correlation is computed in order to calculate the time delay between two signals. In addition, PHAT weighting function can be applied to significantly improve the accuracy of the estimation. However, FFT and IFFT operations in the PHAT weighting function occupy more than half of the area of the sound source localization system. Thus efficient FFT and IFFT designs are essential for the IP implementation of sound source localization system. In this paper, we propose an efficient FFT/IFFT design method based on the characteristics of human voice.