• Title/Summary/Keyword: IC package

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FE-SEM Image Analysis of Junction Interface of Cu Direct Bonding for Semiconductor 3D Chip Stacking

  • Byun, Jaeduk;Hyun, June Won
    • Journal of the Korean institute of surface engineering
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    • v.54 no.5
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    • pp.207-212
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    • 2021
  • The mechanical and electrical characteristics can be improved in 3D stacked IC technology which can accomplish the ultra-high integration by stacking more semiconductor chips within the limited package area through the Cu direct bonding method minimizing the performance degradation to the bonding surface to the inorganic compound or the oxide film etc. The surface was treated in a ultrasonic washer using a diamond abrasive to remove other component substances from the prepared cast plate substrate surface. FE-SEM was used to analyze the bonding characteristics of the bonded copper substrates, and the cross section of the bonded Cu conjugates at the sintering junction temperature of 100 ℃, 150 ℃, 200 ℃, 350 ℃ and the pressure of 2303 N/cm2 and 3087 N/cm2. At 2303 N/cm2, the good bonding of copper substrate was confirmed at 350 ℃, and at the increased pressure of 3087 N/cm2, the bonding condition of Cu was confirmed at low temperature junction temperature of 200 ℃. However, the recrystallization of Cu particles was observed due to increased pressure of 3087 N/cm2 and diffusion of Cu atoms at high temperature of 350 ℃, which can lead to degradation in semiconductor manufacturing.

A Polymer-based Capacitive Air Flow Sensor with a Readout IC and a Temperature Sensor

  • Kim, Wonhyo;Lee, Hyugman;Lee, Kook-Nyeong;Kim, Kunnyun
    • Journal of Sensor Science and Technology
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    • v.28 no.1
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    • pp.1-6
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    • 2019
  • This paper presents an air flow sensor (AFS) based on a polymer thin film. This AFS primarily consists of a polymer membrane attached to a metal-patterned glass substrate and a temperature-sensing element composed of NiCr. These two components were integrated on a single glass substrate. The AFS measures changes in capacitance caused by deformation of the polymer membrane based on the air flow and simultaneously detects the temperature of the surrounding environment. A readout integrated circuit (ROIC) was also fabricated for signal processing, and an ROIC chip, 1.8 mm by 1.9 mm in size, was packaged with an AFS in the form of a system-in-package module. The total size of the AFS is 1 by 1 cm, and the diameter and thickness of the circular-shaped polymer membrane are 4 mm and $15{\mu}m$, respectively. The rate of change of the capacitance is approximately 11.2% for air flows ranging between 0 and 40 m/s.

Automatic assessment of post-earthquake buildings based on multi-task deep learning with auxiliary tasks

  • Zhihang Li;Huamei Zhu;Mengqi Huang;Pengxuan Ji;Hongyu Huang;Qianbing Zhang
    • Smart Structures and Systems
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    • v.31 no.4
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    • pp.383-392
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    • 2023
  • Post-earthquake building condition assessment is crucial for subsequent rescue and remediation and can be automated by emerging computer vision and deep learning technologies. This study is based on an endeavour for the 2nd International Competition of Structural Health Monitoring (IC-SHM 2021). The task package includes five image segmentation objectives - defects (crack/spall/rebar exposure), structural component, and damage state. The structural component and damage state tasks are identified as the priority that can form actionable decisions. A multi-task Convolutional Neural Network (CNN) is proposed to conduct the two major tasks simultaneously. The rest 3 sub-tasks (spall/crack/rebar exposure) were incorporated as auxiliary tasks. By synchronously learning defect information (spall/crack/rebar exposure), the multi-task CNN model outperforms the counterpart single-task models in recognizing structural components and estimating damage states. Particularly, the pixel-level damage state estimation witnesses a mIoU (mean intersection over union) improvement from 0.5855 to 0.6374. For the defect detection tasks, rebar exposure is omitted due to the extremely biased sample distribution. The segmentations of crack and spall are automated by single-task U-Net but with extra efforts to resample the provided data. The segmentation of small objects (spall and crack) benefits from the resampling method, with a substantial IoU increment of nearly 10%.

Optimal pressure and temperature for Cu-Cu direct bonding in three-dimensional packaging of stacked integrated circuits

  • Seunghyun Yum;June Won Hyun
    • Journal of the Korean institute of surface engineering
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    • v.56 no.3
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    • pp.180-184
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    • 2023
  • Scholars have proposed wafer-level bonding and three-dimensional (3D) stacked integrated circuit (IC) and have investigated Cu-Cu bonding to overcome the limitation of Moore's law. However, information about quantitative Cu-Cu direct-bonding conditions, such as temperature, pressure, and interfacial adhesion energy, is scant. This study determines the optimal temperature and pressure for Cu-Cu bonding by varying the bonding temperature to 100, 150, 200, 250, and 350 ℃ and pressure to 2,303 and 3,087 N/cm2. Various conditions and methods for surface treatment were performed to prevent oxidation of the surface of the sample and remove organic compounds in Cu direct bonding as variables of temperature and pressure. EDX experiments were conducted to confirm chemical information on the bonding characteristics between the substrate and Cu to confirm the bonding mechanism between the substrate and Cu. In addition, after the combination with the change of temperature and pressure variables, UTM measurement was performed to investigate the bond force between the substrate and Cu, and it was confirmed that the bond force increased proportionally as the temperature and pressure increased.

Intermetallic Compound Growth Characteristics of Cu/Ni/Au/Sn-Ag/Cu Micro-bump for 3-D IC Packages (3차원 적층 패키지를 위한 Cu/Ni/Au/Sn-Ag/Cu 미세 범프 구조의 열처리에 따른 금속간 화합물 성장 거동 분석)

  • Kim, Jun-Beom;Kim, Sung-Hyuk;Park, Young-Bae
    • Journal of the Microelectronics and Packaging Society
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    • v.20 no.2
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    • pp.59-64
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    • 2013
  • In-situ annealing tests of Cu/Ni/Au/Sn-Ag/Cu micro-bump for 3D IC package were performed in an scanning electron microscope chamber at $135-170^{\circ}C$ in order to investigate the growth kinetics of intermetallic compound (IMC). The IMC growth behaviors of both $Cu_3Sn$ and $(Cu,Ni,Au)_6Sn_5$ follow linear relationship with the square root of the annealing time, which could be understood by the dominant diffusion mechanism. Two IMC phases with slightly different compositions, that is, $(Cu,Au^a)_6Sn_5$ and $(Cu,Au^b)_6Sn_5$ formed at Cu/solder interface after bonding and grew with increased annealing time. By the way, $Cu_3Sn$ and $(Cu,Au^b)_6Sn_5$ phases formed at the interfaces between $(Cu,Ni,Au)_6Sn_5$ and Ni/Sn, respectively, and both grew with increased annealing time. The activation energies for $Cu_3Sn$ and $(Cu,Ni,Au)_6Sn_5$ IMC growths during annealing were 0.69 and 0.84 eV, respectively, where Ni layer seems to serve as diffusion barrier for extensive Cu-Sn IMC formation which is expected to contribute to the improvement of electrical reliability of micro-bump.

Reliability of COF Flip-chip Package using NCP (NCP 적용 COF 플립칩 패키지의 신뢰성)

  • Min, Kyung-Eun;Lee, Jun-Sik;Jeon, Je-Seog;Kim, Mok-Soon;Kim, Jun-Ki
    • Proceedings of the KWS Conference
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    • 2010.05a
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    • pp.74-74
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    • 2010
  • 모바일 정보통신기기를 중심으로 전자패키지의 초소형화, 고집적화를 위해 플립칩 공법의 적용이 증가되고 있는 추세이다. 플립칩 패키징 접합소재로는 솔더, ICA(Isotropic Conductive Adhesive), ACA(Anisotropic Conductive Adhesive), NCA(Non Conductive Adhesive) 등과 같은 다양한 접합소재가 사용되고 있다. 최근에는 언더필을 사용하는 플립칩 공법보다 미세피치 대응성을 위해 NCP를 이용한 플립칩 공법에 대한 요구가 증가되고 있는데, NCP의 상용화를 위해서는 공정성과 함께 신뢰성 확보가 필요하다. 본 연구에서는 LDI(LCD drive IC) 모듈을 위한 COF(Chip-on-Film) 플립칩 패키징용 NCP 포뮬레이션을 개발하고 이를 적용한 COF 패키지의 신뢰성을 조사하였다. 테스트베드는 면적 $1.2{\times}0.9mm$, 두께 $470{\mu}m$, 접속피치 $25{\mu}m$의 Au범프가 형성된 플리칩 실리콘다이와 접속패드가 Sn으로 finish된 폴리이미드 재질의 flexible 기판을 사용하였다. NCP는 에폭시 레진과 산무수물계 경화제, 이미다졸계 촉매제를 사용하여 다양하게 포뮬레이션을 하였다. DSC(Differential Scanning Calorimeter), TGA(Thermogravimetric Analysis), DEA(Dielectric Analysis) 등의 열분석장비를 이용하여 NCP의 물성과 경화거동을 확인하였으며, 본딩 후에는 보이드를 평가하고 Peel 강도를 측정하였다. 최적의 공정으로 제작된 COF 패키지에 대한 HTS (High Temperature Stress), TC (Thermal Cycling), PCT (Pressure Cooker Test)등의 신뢰성 시험을 수행한 결과 양산 적용 가능 수준의 신뢰성을 갖는 것을 확인할 수 있었다.

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A Study on the Cure Behavior of Epoxy Molding Compound (Epoxy Molding Compound의 경화거동에 관한 연구)

  • 윤상영;오명숙;박내정
    • Polymer(Korea)
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    • v.24 no.6
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    • pp.837-844
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    • 2000
  • The cure behavior of commercial epoxy molding compounds (EMC) commonly used for IC package was studied at constant cure temperatures as well as at constant heating rates using differential scanning calorimetry (DSC), rheometer, and dielectric analyzer (DEA). The cure kinetics were obtained using autocatalytic reaction model according to the Ryan Dutta method after assuming m+n equal to 2. The prediction of reaction rates by the model equation corresponded well to experimental data at all temperatures except for 10$0^{\circ}C$. The phase transitions such as gelation and vitrification occurred during network formation. At each isothermal cure temperature, $T_{g}$ was measured in accordance with cure time, and the vitrification point was attained when $T_{g}$ was equal to $T_{cure}$. The temperature dependence of gel points and vitrification points showed good agreement with Arrhenius relation. DEA using parallel plate electrode was effective for the monitoring of EMC cure. we knew that if the resin systems are materials of comparable quality, $_{gel}$$T_{g}$ is constant regardless of accelerator concentration in TTT (Time-Temperature-Transformation) diagram.

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Development of an Effective Defect Classification System for Inspection of QFN Semiconductor Packages (QFN 반도체 패키지의 외형 결함 검사를 위한 효과적인 결함 분류 시스템 개발)

  • Kim, Hyo-Jun;Lee, Jung-Seob;Joo, Hyo-Nam;Kim, Joon-Seek
    • Journal of the Institute of Convergence Signal Processing
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    • v.10 no.2
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    • pp.120-126
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    • 2009
  • There are many different types of surface defects on semiconductor Integrated Chips (IC's) caused by various factors during manufacturing process, such as cracks, foreign materials, chip-outs, chips, and voids. These defects must be detected and classified by an inspection system for productivity improvement and effective process control. Among defects, in particular, foreign materials and chips are the most difficult ones to classify accurately. A vision system composed of a carefully designed optical system and a processing algorithm is proposed to detect and classify the defects on QFN(Quad Flat No-leads) packages. The processing algorithm uses features derived from the defect's position and brightness value in the Maximum Likelihood classifier and the optical system is designed to effectively extract the features used in the classifier. In experiments we confirm that this method gives more effective result in classifying foreign materials and chips.

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Effect of Intermetallic Compounds Growth Characteristics on the Shear Strength of Cu pillar/Sn-3.5Ag Microbump for a 3-D Stacked IC Package (3차원 칩 적층을 위한 Cu pillar/Sn-3.5Ag 미세범프 접합부의 금속간화합물 성장거동에 따른 전단강도 평가)

  • Kwak, Byung-Hyun;Jeong, Myeong-Hyeok;Park, Young-Bae
    • Korean Journal of Metals and Materials
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    • v.50 no.10
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    • pp.775-783
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    • 2012
  • The effect of thermal annealing on the in-situ growth characteristics of intermetallics (IMCs) and the mechanical strength of Cu pillar/Sn-3.5Ag microbumps are systematically investigated. The $Cu_6Sn_5$ phase formed at the Cu/solder interface right after bonding and grew with increased annealing time, while the $Cu_3Sn$ phase formed at the $Cu/Cu_6Sn_5$ interface and grew with increased annealing time. IMC growth followed a linear relationship with the square root of the annealing time due to a diffusion-controlled mechanism. The shear strength measured by the die shear test monotonically increased with annealing time. It then changed the slope with further annealing, which correlated with the change in fracture modes from ductile to brittle at a critical transition time. This is ascribed not only to the increasing thickness of brittle IMCs but also to the decreasing thickness of the solder, as there exists a critical annealing time for a fracture mode transition in our thin solder-capped Cu pillar microbump structures.

Recent Advances in Fine Pitch Cu Pillar Bumps for Advanced Semiconductor Packaging (첨단 반도체 패키징을 위한 미세 피치 Cu Pillar Bump 연구 동향)

  • Eun-Chae Noh;Hyo-Won Lee;Jeong-Won Yoon
    • Journal of the Microelectronics and Packaging Society
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    • v.30 no.3
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    • pp.1-10
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    • 2023
  • Recently, as the demand for high-performance computers and mobile products increases, semiconductor packages are becoming high-integration and high-density. Therefore, in order to transmit a large amount of data at once, micro bumps such as flip-chip and Cu pillar that can reduce bump size and pitch and increase I/O density are used. However, when the size of the bumps is smaller than 70 ㎛, the brittleness increases and electrical properties decrease due to the rapid increase of the IMC volume fraction in the solder joint, which deteriorates the reliability of the solder joint. Therefore, in order to improve these issues, a layer that serves to prevent diffusion is inserted between the UBM (Under Bump Metallization) or pillar and the solder cap. In this review paper, various studies to improve bonding properties by suppressing excessive IMC growth of micro-bumps through additional layer insertion were compared and analyzed.