• Electronics and Telecommunications Trends
• /
• v.4 no.4
• /
• pp.108-134
• /
• 1989

본 고는 현재 공중회선망을 이용한 PC 통신에 필수장비인 모뎀을 구성하는 2,400bps Modem Chip Set을 비교하였다. 현재 널리 사용되는 Modem Chip Set들은 주로 2-3개 Chip으로 구성되며, 이것들을 사용하여 완전한 2,400bps Modem을 구성할 수 있다. 이러한 모뎀용 IC는 PC통신뿐만 아니라 휴대용 Terminal, 차량추적시스팀, 휴대용 전화기, 각종 원격검침계량기 등에서와 같이 그 사용범위가 다양화되고 있는 추세이다.

• ETRI Journal
• /
• v.32 no.2
• /
• pp.327-329
• /
• 2010

A fully integrated small form-factor HBT power amplifier (PA) was developed for UMTS Tx applications. For practical use, the PA was implemented with a well configured bottom dimension, and a CMOS control IC was added to enable/disable the HBT PA. By using helix-on-pad integrated passive device output matching, a chip-stacking technique in the assembly of the CMOS IC, and embedding of the bulky inductive lines in a multilayer substrate, the module size was greatly reduced to 2 mm ${\times}$ 2.2 mm. A stage-bypass technique was used to enhance the efficiency of the PA. The PA showed a low idle current of about 20 mA and a PAE of about15% at an output power of 16 dBm, while showing good linearity over the entire operating power range.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.73-76
• /
• 2002

In this paper we present an integrated Hail sensor It for fan motors, fabricated in industrial bipolar process. As a discrete Hall sensor and signal processing circuitry In the fan motor system were Integrated into single chip a temperature dependence of Hall sensitivity and Hall offset voltage can be compensated and cancelled by on-chip circuitry. We Propose a novel temperature compensation of Hall sensitivity with negative temperature coefficient (TC) using the differential amplifier gain with Positive TC. After a package of the chip was sealed using a plastic Package 20 Pins, the thermal and magnetic characteristics were investigated. The obtained experimental results are in agreement with analytical predictions and have more excellent performance than\ulcorner conventional the fan motor system using discrete Hall sensor.

• ETRI Journal
• /
• v.36 no.4
• /
• pp.643-653
• /
• 2014

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

• Proceedings of the IEEK Conference
• /
• 2002.07c
• /
• pp.1984-1987
• /
• 2002

This paper describes the design and implementation of a single-chip digitally synthesized 0-35MHz agile function generator. The chip comprises an integrated direct digital synthesizer (DDS) with a 10-bit on- chip digital-to-analog converter (DAC) using an n-well single-poly triple-metal 0.5-$\mu\textrm{m}$ CMOS technology. The main features of the chip include maximum clock frequency of 100 MHz at 3.3-V supply voltage, 32-bit frequency tuning word resolution, 12-bit phase tuning word resolution, and an on-chip 10-bit DAC. The chip provides sinusoidal, ramp, saw-tooth, and random waveforms with phase and frequency modulation, and power-down function. At 100-MHz clock frequency, the chip covers a bandwidth from dc to 35 MHz in 0.0233-Hz frequency steps with 190-ns frequency switching speed. The complete chip occupies 12-mm$^2$die area and dissipates 0.4 W at 100-MHz clock frequency.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.56 no.7
• /
• pp.1282-1287
• /
• 2007

We investigated the damage of the CMOS IC which manufactured three different technologies by high power microwave. The tests separated the two methods in accordance with the types of the CMOS IC located inner waveguide. The only CMOS IC which was located inner waveguide was occurred breakdown below the max electric field (23.94kV/m) without destruction but the CMOS IC which was connected IC to line organically was located inner waveguide and it was occurred breakdown and destruction below the max electric field. Also destructed CMOS IC was removed their surface and a chip condition was analyzed by SEM. The SEM analysis of the damaged devices showed onchuipwire and bondwire destruction like melting due to thermal effect. The tested results are applied to the fundamental data which interprets the combination mechanism of the semiconductors from artificial electromagnetic wave environment and are applied to the data which understand electromagnetic wave effects of electronic equipments.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.24 no.6
• /
• pp.1056-1067
• /
• 1987

This paper presents a design procedure for building block integrated circuits that is based on the digraph relaxation model. A set of optimization procedure is prosented for a minimum area and routing-fecsible placement of IC building blocks. Chip area optimization is subject to perimeter and area constraints on the component rectangles in the dissection.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.6
• /
• pp.1283-1288
• /
• 2015

In general, IC chip circuit which is operating a cryptographic computation tends to radiate stronger electromagnetic signal to the outside. By using a power detecter such as a loop antenna near cryptographic device, the encryption key can be identified by probing a electromagnetic signal. To implement a method against non-invasive type attack, multi dielectric slab structure on IC chip to suppress radiated electromagnetic signal was introduced. Multiple dielectric slab was implemented by suitably configured to have the Bragg reflection characteristics, and then the reflection response was computed and verified its effectiveness. As a result, the thickness of the dielectric coating was 2mm and the reflection response characteristics for the vertical incidence was achieved to be 91% level.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.2
• /
• pp.202-211
• /
• 2014

The bulk current injection (BCI) and direct power injection (DPI) method have been established as the standards for the electromagnetic susceptibility (EMS) test. Because the BCI test uses a probe to inject magnetically coupled electromagnetic (EM) noise, there is a significant difference between the power supplied by the radio frequency (RF) generator and that transferred to the integrated circuit (IC). Thus, the immunity estimated by the forward power cannot show the susceptibility of the IC itself. This paper derives the real injected power at the failure point of the IC using the power transfer efficiency of the BCI method. We propose and mathematically derive the power transfer efficiency based on equivalent circuit models representing the BCI test setup. The BCI test is performed on I/O buffers with and without decoupling capacitors, and their immunities are evaluated based on the traditional forward power and the real injected power proposed in this work. The real injected power shows the actual noise power level that the IC can tolerate. Using the real injected power as an indicator for the EMS test, we show that the on-chip decoupling capacitor enhances the EM noise immunity.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.2
• /
• pp.88-93
• /
• 2004

We, for the first time, present novel test patterns and conclusive on-chip data indicating that the variation of coupling capacitance, ${\Delta}C_C$ by crosstalk can be larger than static coupling capacitance, $C_C$. The test chip is fabricated using a generic 150 nm CMOS technology with 7 level metallization. It is also shown that ${\Delta}C_C$ is strongly dependent on the phase of aggressive lines. For antiphase crosstalk ${\Delta}C_C$ is always larger than $C_C$ while for in-phase crosstalk $D_{\Delta}C_C$is smaller than $C_C$.