• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.4
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• pp.85-98
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• 2003

Computational power of IC chip is improved day after day producing IC chips holding co-processor continuously. Also a lot of wireless terminals which IC chip embedded in are produced in order to provide simple and various services in the wireless terminal market. However it is difficult to apply the key distribution protocol under wired communication environment to wireless communication environment. Because the computational power of co-processor embedded in IC chip under wireless communication environment is less than that under wired communication environment. In this paper, we propose the hey distribution protocol appropriate for wireless communication environment which diminishes the computational burden of server and client by using co-processor that performs cryptographic operations and makes up for the restrictive computational power of terminal. And our proposal is satisfied with the security requirements that are not provided in existing key distribution protocol.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.6
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• pp.633-643
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• 2013

GDS format files, as well as layout of the chip are noticeably needed so as to analyze the PDN (Power Delivery Network) inside of IC; however, commercial IC in the market has not supported design information which is layout of IC. Within this, in terms of IC having on-chip PDN, characteristic of inside PDN of the chip is a core parameter to predict generated noise from power/ground planes. Consequently, there is a need to scrutinize extraction method for unknown PDN of the chip in this paper. To extract PDN of the chip without IC circuit information, the de-embedding test vehicle is fabricated based on IEC62014-3. Further more, the extracted inside PDN of chip from de-embedding technique adopts the Co-simulation model which composes PCB, QFN (Quad-FlatNo-leads) Package, and Chip for the PDN, applied Co-simulation model well corresponds with impedance from measured S-parameters up to 4 GHz at common measured and simulated points.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.131-137
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• 2016

In this paper, we analyze the impedance analysis of vertical interconnection through-silicon vias (TSV) that is being studied for the purpose of improving the degree of integration and an electric feature in 3D IC. Also, it is to improve the performance and the degree of integration of the three-dimensional integrated circuit system which can exceed the limits of conventional two-dimensional a IC. In the future, TSV technology in full-chip 3-dimensional integrated circuit system design is very important, and a study on the electrical characteristics of the TSV for high-density and high-bandwidth system design is very important. Therefore, we study analyze the impedance influence of the TSV in accordance with the distance and frequency in a multiple TSV-to-TSV for the purpose of designing a full-chip three-dimensional IC. The results of this study also are applicable to semiconductor process tools and designed for the manufacture of a full-chip 3D IC.

• Journal of the Institute of Convergence Signal Processing
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• v.25 no.1
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• pp.46-51
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• 2024

Drone was first used for military purposes but as the range of use has recently expanded. It is being widely used in various industrial fields such as agriculture, service, logistics, and leisure. Lithium polymer batteries are lightweight and highly efficient, so they are mainly used as power supplies for drones. Accordingly, the need for lightweight and high energy density lithium polymer batteries has increased in order to supply stable power to drone. However, lithium polymer batteries can lead to ignition and explosion due to overcharging, short circuit, etc., so they must be used with a protective circuit installed. The protection circuit consists of a protection IC that monitors the voltage of the lithium polymer battery and a dual N-channel MOSFET that acts as a switch in case of overcharge and overdischarge. Therefore, this paper was implemented in one package form using a battery protection IC and a MOSFET semiconductor die chip serving as a switch. When implemented as a one chip package IC, at least 67% of savings compared to existing parts can be achieved.

• Resources Recycling
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• v.3 no.1
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• pp.38-43
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• 1994

The separation of valuable metals from IC chip scrap generated by domestic electronic company was carried out using the mechanical beneficiation such as shredding, crushing, screening and magnetic separation. The distribution of metals in various sizes of crushed IC chip scrap was investigated and metals present in crushed products was separated with the magnetic separator. The particle size distribution of crushed IC chip scrap was 7.5% for +3mm, 17.0% for 3~1mm and 75.5% for -1mm. The weight loss of crushed IC chip scrap was 18% when roasted at $700^{\circ}C$. The content of metals was 96% for +3~1mm, 13% for 1~0.595mm, 3.7% for 0.95~0.5. Au of 99% was present in -1mm crushed IC chip scrap. Ni, Fe, Cu, Sn and Pb were separated from crushed IC chip scrap by the magnetic separator under 700 and 2, 500 Gauss.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.93-100
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• 2003

The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. These latter technologies have not kept pace with the IC scaling trends, resulting in a so-called“interconnect technology gap”. Multilayer thin film technology is proposed as a“bridge”- technology between the very high density IC technology and the coarse standard PCB technology. It is also a key enabling technology for the realisation of true“System-in-a-Package”(SIP) solutions, combining multiple“System-on-a-Chip”(SOC) IC's with other components and also integrating passive components in its layers. A further step is to use this technology to realise new functionalities on top of active wafers. These additional“above-IC”processed layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.203-211
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• 1996

This paper describes CAD tools for the construction of image database in IC chip analysis CAD system. For IC chip analysis by high-resolution microscopy, the image database is essential to manage more than several thousand images. But manual database construction is error-prone and time-consuming. In order to solve this problem, we develop a set of CAD toos that include image grabber to capture chip images, image editor to make the whole chip image database from the grabbed images, and image divider to reconstruct the database that consists of evenly overlapped images for efficient region search. we also develop an interactive pattern matching method for user-friendly image editing, and a heuristic region search method for fast image division. The tools are developed with a high-performance graphic hardware with JPEG image comparession chip to process the huge color image data. The tools are under the field test and experimental resutls show that the database construction time can be redcued in 1/3 compared to manual database construction.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.17 no.3
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• pp.14-19
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• 2008

In the semiconductor IC(Integrated Circuit) package, the top surface of silicon chip is directly attached to the area of the leadframe with a double-sided adhesive layer, in which the base layer have the upper adhesive layer and the lower adhesive layer. The IC package structure has been known to encounter a thermo-mechanical failure mode such as delamination. This failure mode is due to the residual stress on the adhesive surface of silicon chip and leadframe in the curing-cooling process. The induced thermal stress in the curing process has an influence on the cooling residual stress on the silicon chip and leadframe. In this paper, for the minimization of the chip surface damage, the adhesive topologies on the silicon chip are studied through the finite element analysis(FEA).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.474-480
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• 2003

We designed and tested a new scan driver output stage. Compared to conventional CMOS structured scan driver IC′s, the new NMOSFET-only scan driver circuit can reduce the chip area and therefore, the chip cost considerably. We confirmed the circuit operation with open drain power NMOSFET IC′s by driving 2"PDP test panel. We defined critical device parameters and their optimization methods lot the best circuit performance.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1141-1144
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• 2003

For proper communication with various types of IC-Card, multiple IC-Card interface complying with the IC-Card standard (ISO7816) is embedded and realized as a peripheral on the 32-bit RISC based system-on-a-chip. It provides the generation of either 3.3V or 5V power supply for the operation of the inserted IC-Card as well. IC-Card interface is divided into an analog front-end (AFE) and a digital back-end (DBE). The embedded DC-DC converters suitable for driving IC-Cards are incorporated in the AFE. The chip design for multiple IC-Card interface is implemented on a standard 0.35${\mu}{\textrm}{m}$ triple-metal double-poly CMOS process and is packaged in a 352-pin plastic ball grid array (PBGA). The total gate count is about 400,000, excluding the internal memory. Die area is 7890${\mu}{\textrm}{m}$ $\times$ 7890${\mu}{\textrm}{m}$.