• Journal of the Korea Society of Computer and Information
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• v.20 no.11
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• pp.1-8
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• 2015

Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.157-163
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• 2002

A new flash EEPROM device with p^＋ poly-Si control gate and n^＋ poly-Si floating side gate was fabricated and characterized. The n^＋ poly-Si gate is formed on both sides of the p^＋ poly-Si gate, and controls the underneath channel conductivity depending on the number of electron in it. The cell was programmed by hot-carrier-injection at the drain extension, and erased by direct tunneling. The proposed EEPROM cell can be scaled down to 50 nm or less. Shown were measured programming and erasing characteristics. The channel resistance with the write operation was increased by at least 3 times.

• Journal of the Korean institute of surface engineering
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• v.29 no.5
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• pp.357-362
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• 1996

Several applications of radio-frequency (RF) thermal plasma to film formation are reviewed. Three types of injection plasma processing (IPP) technique are first introduced for the deposition of materials. Those are thermal plasma chemical vapor deposition (CVD), plasma flash evaporation, and plasma spraying. Radio-frequency (RF) plasma and hybrid (combination of RF and direct current(DC)) plasma are next introduced as promising thermal plasma sources in the IPP technique. Experimental data for three kinds of processing are demonstrated mainly based on our recent researches of depositions of functional materials, such as high temperature semiconductor SiC and diamond, ionic conductor $ZrO_2-Y_2O_3$ and high critical temperature superconductor $YBa_2Cu_3O_7-x$. Special emphasis is given to thermal plasma flash evaporation, in which nanometer-scaled clusters generated in plasma flame play important roles as nanometer-scaled clusters as deposition species. A novel epitaxial growth mechanism from the "hot" clusters namely "hot cluster epitaxy (HCE)" is proposed.)" is proposed.osed.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.879-882
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• 1999

The effects of the substrate bias on the performance of programming erasing in p-channel flash memory cell have been investigated. It is found that applying positive substrate bias can improve the programming and erasing speed. This improvements can be explained by Substrate Current Induced Hot Electron Injection. From the results, we can confirm that BTB programming method is better in programming and erasing speed than CHE programming method.

• Proceedings of the Korean Information Science Society Conference
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• 2007.10a
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• pp.245-246
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• 2007

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.11-20
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• 2008

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.80-83
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• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by $0.35\;{\mu}m$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the two-bits per cell operation, charges must be locally trapped in the nitride layer above the channel near the junction. Channel hot electron (CHE) injection for programming can operate in multi-bit using localized trap in nitride film. CHE injection in our devices is achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The multi-bit operation which stores two-bit per cell is investigated with a reverse read scheme. Also, hot hole injection for fast erasing is used. Due to the ultra-thin gate dielectrics, our results show many advantages which are simpler process, better scalability and lower programming voltage compared to any other two-bit storage flash memory. This fabricated structure and programming characteristics are shown to be the most promising for the multi-bit flash memory.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.10b
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• pp.229-230
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• 2002

This paper presents the hot spot behaviors on the rubbing surface of ventilated disk brake by using finite element method. The depth of asperities on the rubbing surface is usually $2-3\;{\mu}m$ so the real contact area is microscopically. Non-uniform contacts between the disk and the pads lead to high local temperatures, which may cause the material degradation, and develops hot spots, thermal cracking, and brake system failures at the end. High contact asperity flash temperatures in rubbing systems, which is strongly related to the hot spot. It was generally known that high temperature over about $700^{\circ}C$ may form martensite on the cast iron which is material for automotive disk brakes. In this paper, the contact stress, temperature distribution and strain have been presented for the specific asperities of real contact area microscopically by using coupled thermal-mechanical analysis technique.

• Transactions of Materials Processing
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• v.11 no.2
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• pp.179-186
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• 2002

In the finite element analysis of metal forming Processes using general Lagrangian formulation, element nodes in the mesh move and elements are distorted as the material is deformed. The excessive degeneracy of mesh interrupts finite element analysis and thus increases the error of plastic deformation energy, In this study, a remeshing scheme using so-called mesh compression method is proposed to effectively analyze the flash which is generated usually in hot forging processes. In order to verify the effectiveness of the method, several examples are tested in two-dimensional and three-dimensional problems.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06a
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• pp.248-249
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• 2007