• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.638-643
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• 2003

Channel width dependence of hot-carrier effect in nMOSFET with shallow trench isolation is analyzed. $I_{sub}$- $V_{G}$ and $\Delta$ $I_{ㅇ}$ measurement data show that MOSFETs with narrow channel-width are more susceptible to the hot-carrier degradation than MOSFETs with wide channel-width. By analysing $I_{sub}$/ $I_{D}$, linear $I_{D}$- $V_{G}$ characteristics, thicker oxide-thickness at the STI edge is identified as the reason for the channel-width dependent hot-carrier degradation. Using the charge-pumping method, $N_{it}$ generation due to the drain avalanche hot-carrier (DAHC) and channel hot-electron (CHE) stress are compared. are compared.

• Journal of the Korean Society for Precision Engineering
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• v.28 no.1
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• pp.63-72
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• 2011

In recent years, hot-stamped components are more increasingly used in the automotive industry in order to reduce weight and to improve the strength of vehicles. In hot stamping process, blank is hot formed and press hardened in a tool. However, in hot stamping without cooling channel, temperature of the tool increases gradually in mass production thus cannot meet the critical cooling rate to obtain high strength over 1500MPa. Warpage occurs in the hot stamped component due to non-uniform stress state caused by unbalanced cooling. Therefore, tools should be uniformly as well as rapidly cooled down by the coolant which flows through cooling channel. In this paper, optimal design method of cooling channel to obtain uniform and high strength of the component is proposed. Optimized cooling channel is applied to the hot press V-bending process. As a result of measuring strength, hardness and microstructure of the hot formed parts, it is known that the design methodology of cooling channel is effective to the hot stamping process.

• Nuclear Engineering and Technology
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• v.20 no.2
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• pp.80-87
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• 1988

Predicted in this paper are flow distributions in average and hot channels of the reactor core during small and large break LOCAs. Also estimated based on REALP5/MOD2 calculations are the effects of cross flow between channels on LOCA analysis results. It has been so far generally accepted that a single average channel is sufficient for small break LOCA core hydraulic modelling. However, based on these calculation results, hot channel modeling (two channel modeling) is found necessary in order to guarantee more reliable and conservative results. In large break LOCA blowdown phase, the hot channel thermal hydraulics is worse than that of average channel in both cases with the without consideration of cross flow.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.11
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• pp.1267-1273
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• 2009

Hot press forming can produce high-strength components by rapidly cooling between closed punch and die after hot forming using quenchable boron steel austenized in a furnace. In the hot press forming process, the cooling rate is influenced by the size, position and arrangement of the cooling channel and the file condition of cooling water in the die. Also, mechanical properties of the final components and operation time are related to cooling rate. Therefore, the design of optimized cooling channel is one of the most important works. In this paper, the effect of position and size of the cooling channel on the cooling rate was investigated by using design of experiment and FE analysis in hot press bending process. Therefore the optimum cooling channel ratio was presented in the HPB.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.889-893
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• 2015

In this work, the characteristics of GIDL current in nanowire GAA MOSFET with different channel width and hot carrier stress. When the gate length is fixed as a 250nm the GIDL current with different channel width of 10nm, 50nm, 80nm, and 130nm have been measured and analyzed. From the measurement, the GIDL is increased as the channel width decreaes. However, the derive current is increased as the channel width increases. From measurement results after hot carrier stress, the variation of GIDL current is increased with decreasing channel width. Finally, the reasons for the increase of GIDL current with decreasing channel width and r device. according to hot carrier stress GIDL's variation shows big change when width and the increase of GIDL current after hot carrier stress are confirmed through the device simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1649-1655
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• 2005

For systems with coexisting cellular and hot-spot cells in broadband orhogonal frequency and code division multiplexing (OFCDM) systems, a suitable cell search algorithm is proposed fur the common pilot channel (CPICH) in the forward link using separated I/Q channel cell specific codes(CSSC), in which the cellular cell specific scrambling code (CCSSC) is assigned to the in-phase (Q) pilot channel of all cellular cells, and the exclusive hot-spot cell specific scrambling code (HSCSSC) group is assigned to the quadrature (Q) pilot channel of all hot-spot cells. Therefore, the proposed algorithm enables a mobile station (MS) to search quickly for the most desirable hot-spot cell due to reducing the effect of CCSSC, when a MS wants to use a mobile internet. The computer simulation results show that the proposed cell search algorithm can achieve faster cell search time performance, compared to conventional cell search methods.

• Transactions of Materials Processing
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• v.25 no.4
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• pp.242-247
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• 2016

CFD simulation with FlowVision^® is used to evaluate the capability of cooling channel in hot press forming dies. Two different types of cooling channels, dry drilled and pocket types are considered for comparison. Two different approaches for simulating cooling channel are considered. One is single-phase velocity calculation for coolant only and the other is multiphase thermal and velocity calculation for die, blank and coolant all together. Both approaches show better cooling performance in pocket type cooling channel. Also both approaches show their own effectiveness in designing cooling channel of hot press forming dies.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.130-138
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• 1996

The size of a device needs to scale down to increase its integrity and speed. As the size of the device is reduced, the hot-carrier degradation that severely effects on device reliabilty is concerned. In this paper, sub-micron buried-channel P-MOSFETs were fabircated, and the hot-carrier effects were invetigated. Also the hot-carrier effect in the buired-channel P-MOSFETs and the surface-channel P-MOSFETs were compared with simulation programs using SUPREM-4 and MINIMOS-4. This paper showed that the electric characteristics of sub-micron P-MOSFET are different from those of N-MOSFET. Also it showed that the punchthrough voltage ( $V_{pt}$ ) was abruptly drop after applying the stress and became almost 0V when the channel lengths were shorter than 0.6.mu.m. The lower punchthrough voltage causes the device to operte poorly by the deterioration of cut-off characteries in the switching mode. We can conclude that the buried channel P-MOSFET for CMOS circuits has a limit of the channel length to be around 0.6.mu.m.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1367-1369
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• 1998

To achieve the ULSI goals of higher density, greater performance and operation speed have been scaled down. However, the reduction of channel length cause undesirable problems such as drop of punchthrough voltage, hot-carrier degradation and high leakage current, etc.. It is shown that the device characteristics depend on process parameters. In this Paper, we catched hold of trends of hot-carrier effects and punchthrough voltages due to variation of some process parameters such as LDD doses(P), spacer lengths, channel doses($BF_2$) and $V_T$ adjusting channel implantation energies using design trend curve (DTC). As the LDD and channel doses increased, hot-carrier phenomena became more severe, and punchthrough voltage was decreased. It were represented that punchthrough and hot carrier effects were critically depend on LDD and channel doses.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.12
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• pp.53-58
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• 1991

Hot-carrier induced degradation has been studied for the BF$_2$ ion-implanted surface-channel LDD(P$^{+}$ polysilicon gate) PMOSFET in comparison to the buried-channel structure(N$^{+}$ polysilicon gate) PMOSFET. The conditions for maximum degradation better correlated to I$_{g}$ than I$_{sub}$ for both PMOSFET's. Due to the use of LDD structure on SC-PMOSFET, the substrate current for SC-PMOSFET was shown to be smaller than that of BC-PMOSFET. The gate current was smaller as well, due to the gate material work-function difference between p$^{+}$ and n$^{+}$ polysilicon gates. From the results, it was shown that the surface-channel LDD PMOSFET is more resistant to short channel effect than the buried-channel PMOSFET.