• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.13-18
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• 2007

This paper presents the experimental findings on the different degradation mechanism which depends on the gate oxide thickness in lateral DMOS transistors. For thin oxide devices, the generation of interface states in the channel region and the trapped holes in the drift region is found to be the causes of the device degradation. For thick devices, the generation of interface states in the channel region is found to be the causes of the device degradation. We confirmed the different degradation mechanism using device simulation. From the comparison of device degradation under DC and AC stress, it is found that the device degradation is more significant under DC stress than one under AC stress. The device degradation under AC stress is more significant in high frequency. Therefore the hot carrier induced degradation should be more carefully considered in the design of RF LDMOS transistors and circuit design.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.1
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• pp.82-89
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• 2017

In this work, InGaZnO thin film transistors with Ni, Al and ITO source and drain electrode materials were fabricated to analyze a hot carrier induced device degradation according to the electrode materials. From the electrical measurement results with electrode materials, Ni device shows the best electrical performances in terms of mobility, subthreshold swing, and $I_{ON}/I_{OFF}$. From the measurement results on the device degradation with source and drain electrode materials, Al device shows the worst device degradation. The threshold voltage shifts with different channel widths and stress drain voltages were measured to analyze a hot carrier induced device degradation mechanism. Hot carrier induced device degradation became more significant with increase of channel widths and stress drain voltages. From the results, we found that a hot carrier induced device degradation in InGaZnO thin film transistors was occurred with a combination of large channel electric field and Joule heating effects.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.94-100
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• 2017

Stress drain bias dependent current model is proposed for sub-70-nm p-channel metal-oxide semiconductor field-effect transistors (pMOSFETs) under drain-avalanche-hot-carrier (DAHC-) mechanism. The proposed model describes the both on-current and off-current degradation by using two device parameters: channel length variation (${\Delta}L_{ch}$) and threshold voltage shift (${\Delta}V_{th}$). Also, it is a simple and effective model of predicting reliable circuit operation and standby power consumption.

• Journal of the Society of Naval Architects of Korea
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• v.45 no.3
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• pp.296-302
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• 2008

Recently, a mesh-size insensitive structural stress definition (structural stress method) is proposed that gives a stress state at weld toe with a relatively large mesh size. The structural stress definition is based on the elementary structural mechanics theory and provides an effective measure of a stress state in front of weld toe. In this study, a fatigue strength assessment for a side shell connection of a container vessel using both the hot spot stress and the Battelle structural stress method was carried out. A consistent approach to compute the extrapolated hot spot stress for design purpose is described and current fatigue guidance is evaluated. Fatigue strength predicted by the two methodologies, e.g. hot spot stress and structural stress approaches, at hot spot locations of a typical ship structure are compared and discussed.

• International Journal of Naval Architecture and Ocean Engineering
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• v.7 no.1
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• pp.10-24
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• 2015

This study introduces a fatigue assessment procedure using mesh-insensitive structural stress method based on the Common Structural Rules for Bulk Carriers by considering important factors, such as mean stress and thickness effects. The fatigue assessment result of mesh-insensitive structural stress method have been compared with CSR procedure based on equivalent notch stress at major hot spot points in the area near the ballast hold for a 180 K bulk carrier. The possibility of implementing mesh-insensitive structural stress method in the fatigue assessment procedure for ship structures is discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.489-492
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• 1999

The effects of alternate bias stress on p-channel poly-Si TPT's has been systematically investigated. It has been shown that the application of alternate bias stress affects device degradation for the negative bias stress as well as device improvement for the positive bias stress. This effects have been related to the hot carrier injection into the gate oxide rather than the generation of defect states within the poly-Si/SiO$_2$ under bias stress.

• 전자공학회논문지 IE
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• v.47 no.1
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• pp.1-5
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• 2010

This paper presents new results of the impact of gate structure on hot-carrier-induced performance degradation in SOI low noise amplifier. Circuit simulations were carried out using the measured S-parameters of H--gate and T-gate SOI MOSFETs and Agilent's Advanced Design System (ADS) to compare the performance of H-gate LNA and T-gate LNA before and after stress. We will discuss the figure of merit for the characterization of low noise amplifier in terms of impedance matching (S11), noise figure, and gain as well as the relation between device degradation and performance degradation of LNA.

• The KIPS Transactions:PartA
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• v.15A no.4
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• pp.211-216
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• 2008

In this paper we fabricated and measured the $0.26{\mu}m$ NMOSFET with wet gate oxide and nitride oxide gate to compare that the charateristics of hot carrier effect, charge to breakdown, transistor Id_Vg curve, charge trapping, and SILC(Stress Induced Leakage Current) using the HP4145 device tester. As a result we find that the characteristics of nitride oxide gate device better than wet gate oxide device, especially hot carrier lifetime(nitride oxide gate device satisfied 30 years, but the lifetime of wet gate oxide was only 0.1 year), variation of Vg, charge to breakdown, electric field simulation and charge trapping etc.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.32-38
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• 2003

This works reports the measurement and analysis results on the hot electron induced device degradation in Gate-All-Around SOI MOSFET's, which were fabricated using commercially available SIMOX material. It is observed that the worst-case condition of the device degradation in nMOSFETs is $V_{GS}$ = $V_{TH}$ due to the higher impact ionization rate when the parasitic bipolar transistor action is activated. It is confirmed that the device degradation is caused by the interface state generation from the extracted degradation rate and the dynamic transconductance measurement. The drain current degradation with the stress gate voltages shows that the device degradation of pMOSFETs is dominantly governed by the trapping of hot electrons, which are generated in drain avalanche hot carrier phenomena.r phenomena.

• Transactions on Electrical and Electronic Materials
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• v.7 no.1
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• pp.1-6
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• 2006

Hot carrier degradation and roll off characteristics of threshold voltage ($V_{t1}$) on NMOSFETs as I/O transistor are studied as a function of Lightly Doped Drain (LDD) structures. Pocket dose and the combination of Phosphorus (P) and Arsenic (As) dose are applied to control $V_{t1}$ roll off down to the $10\%$ gate length margin. It was seen that the relationship between $V_{t1}$ roll off characteristic and substrate current depends on P dopant dose. For the first time, we found that the n-p-n transistor triggering voltage ($V_{t1}$) depends on drain current, and both $I_{t2}$ and snapback holding voltage ($V_{sp}$) depend on the substrate current by characterization with a transmission line pulse generator. Also it was found that the improved lifetime for hot carrier stress could be obtained by controlling the P dose as loosing the $V_{t1}$ roll off margin. This study suggests that the trade-off characteristic between gate length margin and channel hot carrier (CHC) lifetime in NMOSFETs should be determined by considering Electrostatic Discharge (ESD) characteristic.