• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 춘계학술대회 논문집
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• pp.90-93
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• 1996

The conduction mechanisms of the off-current in low temperature ($\leq$600$^{\circ}C$) processed polycrystalline silicon thin film transistors (LTP poly-Si TFT's) has been systematically studied. Especially, the temperature and bias dependence of the off-current between unpassivated and passivated poly-Si TFT's was investigated and compared. The off-current of unpassivated poly-Si TFT's is due to a resistive current at low gate and drain voltage, thermal emission current at high gate, low drain voltage, and field enhanced thermal emission current in the depletion region near the drain at high gate and drain voltage. After hydrogenation, it was observed that the off-currents were remarkably reduced by plasma-hydrogenation. It was also observed that the off-currents of the passivated poly-Si TFT's are more critically dependent on temperature rather than electric field.

• E2M - 전기 전자와 첨단 소재
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• 제9권10호
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• pp.1001-1007
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• 1996

The conduction mechanisms of the off-current in low temperature (.leq. >$600^{\circ}C$) processed polycrystalline silicon thin film transistors (LTP poly-Si TFT'S) have been systematically studied. Especially, the temperature and bias dependence of the off-current between hydrogenated and nonhydrogenated poly-Si TFT's were investigated and compared. The off-current of nonhydrogenated poly-Si TF's is because of a resistive current at low gate and drain voltage, thermally activated current at high gate and low drain voltage, and Poole-Frenkel emission current in the depletion region near the drain at high gate and drain voltage. After hydrogenation it has shown that the off -current mechanism is caused mainly by thermal activation and that the field-induced current component is suppressed.

• Transactions on Electrical and Electronic Materials
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• 제4권6호
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• pp.32-37
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• 2003

In this paper, the trap characteristics of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4nm and 814nm, which have the gate area 10$\^$-3/ $\textrm{cm}^2$. The stress induced leakage currents will affect data retention, and the stress current and transient current is used to estimate to fundamental limitations on oxide thicknesses.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.209-212
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• 2004

In this paper, The stress induced leakage currents of thin silicon oxides is investigated in the nano scale structure implementation for Soc. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $41\square\;and\;113.4\square,$ which have the channel width x length 10x1um, respectively. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.

• 한국정보통신학회논문지
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• 제15권6호
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• pp.1349-1354
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• 2011

본 연구에서는 CdZnS와 CdTe로 구성되는 이종접합 소자를 제작하고 커패시턴스-전압 특성을 조사하였다. CdS/CdTe 접합의 경우, 역방향 바이어스가 증가함에 따라 공핍층의 폭이 커져 커패시턴스 값이 약간 감소하였으나 CdZnS/CdTe 접합에서는 CdTe 박막 내에서의 공핍층 폭이 바이어스에 크게 영향을 받지 않아 커패시턴스 값이 역방향 바이어스에 따라 거의 변화가 없었다. 바이어스 전압을 인가하지 않은 상태에서의 공핍층 폭은 높은 CdZnS 박막의 비저항 및 낮은 캐리어 농도로 인해 CdS/CdTe 접합보다 CdZnS/CdTe 접합에서 보다 큰 값을 나타내었다. CdZnS/CdTe 태양전지의 개방전압은 Zn의 비율이 커짐에 따라 CdZnS 박막과 CdTe 박막의 전자 친화력 차이의 감소로 인하여 크게 증가하였으나, Zn 비율이 0.35 이상인 경우 오히려 감소함을 알 수 있었다. 또한 CdZnS 박막의 높은 비저항이 태양전지의 직렬저항을 상승시켜 전지의 변환 효율은 오히려 감소함을 알 수 있었다.

• 한국전자파학회논문지
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• 제25권8호
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• pp.795-801
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• 2014

본 논문에서는 2.6 GHz에 설계된 고출력 전력증폭기에 DDBS(Digitally-controlled Dynamic Bias Switching)를 적용하여 평균 전력에서 효율을 개선하였다. DBS는 제어 신호에 따라 전력 증폭기에 두 단계의 드레인 전압을 인가하여 효율을 개선하는 기술이다. DBS의 제어 신호를 디지털로 처리하여 제어가 매우 용이하였다. 2.6 GHz의 중심 주파수와 10 MHz 대역폭, 9.5 dB의 PAPR(Peak-to-Average Power Ratio)을 갖는 64 QAM FDD LTE 신호를 사용하여 측정한 결과, DDBS를 적용하여 전력증폭기의 PAE(Power-Added Efficiency)을 평균 전력 43 dBm에서 40.9 %에서 48 %로 증가시켰다.

• Bulletin of the Korean Chemical Society
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• 제29권2호
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• pp.438-444
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• 2008

A self-assembled monolayer of 2,2'-bipyridine (22BPY) molecules on Au(111) underwent a structural phase transition when the polarity of a bias voltage was switched in scanning tunneling microscopy (STM) experiments. The nature of two bright spots representing each 22BPY molecule on Au(111) in the high-resolution STM images was identified by calculating the partial density plots for a monolayer of 22BPY molecules adsorbed on Au(111) using tight-binding electronic structure calculations. The stacking pattern of the chains of 22BPY molecules on Au(111) was explained by examining the intermolecular interactions between the 22BPY molecules based on first principles electronic structure calculations for a 22BPY dimer, (22BPY)2. The structural instability of the 22BPY molecule arrangement caused by a change in the bias voltage switch was investigated by estimating the adsorbate-surface interaction energy using a point-charge approximation for Au(111).

• ETRI Journal
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• 제15권2호
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• pp.11-25
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• 1993

Interface trap densities at gate oxide/silicon substrate ($SiO_2/Si$) interfaces of metal oxide semiconductor field-effect transistors (MOSFETs) were determined from the substrate bias dependence of the subthreshold slope measurement. This method enables the characterization of interface traps residing in the energy level between the midgap and that corresponding to the strong inversion of small size MOSFET. In consequence of the high accuracy of this method, the energy dependence of the interface trap density can be accurately determined. The application of this technique to a MOSFET showed good agreement with the result obtained through the high-frequency/quasi-static capacitance-voltage (C-V) technique for a MOS capacitor. Furthermore, the effective substrate dopant concentration obtained through this technique also showed good agreement with the result obtained through the body effect measurement.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.108-111
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• 2003

Currently, molecular devices are reported utilizing active self-assembled monolayers containing the nitro group as the active component, which has active redox centers[1]. We confirm the electrical properties of 4,4-di(ethynylphenyl)-2'-nitro-1-benzenethiolate. To deposit the SAM layer onto gold electrode, we transfer the prefabricated Au(111) substrates into a 1mM self-assembly molecules in THF solution. Au(111) substrates were prepared by ion beam sputtering method of gold onto the silicon wafer. As a result, we measured current-voltage curve using ultra high vacuum scanning tunneling microscopy (UHV STM), I-V curve also clearly shows several current peaks between the negative bias region (-0.3958V) and the positive bias region (0.4658V), respectively.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.450-450
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• 2012

In recent days, advances in ZnO-based oxide semiconductor materials have accelerated the development of thin-film transistors (TFTs), which are the building blocks for active matrix flat-panel displays including liquid crystal displays (LCD) and organic light-emitting diodes (OLED). In particular, the development of high-mobility ZnO-based channel materials has been proven invaluable; thus, there have been many reports of high-performance TFTs with oxide semiconductor channels such as ZnO, InZnO (IZO), ZnSnO (ZTO), and InGaZnO (IGZO). The reliability of oxide TFTs can be improved by examining more stable oxide channel materials. In the present study, we investigated the effects of an ALD-deposited water vapor permeation barrier on the stability of ZnO and HfZnO (HZO) thin film transistors. The device without the water vapor barrier films showed a large turn-on voltage shift under negative bias temperature stress. On the other hand, the suitably protected device with the lowest water vapor transmission rate showed a dramatically improved device performance. As the value of the water vapor transmission rate of the barrier films was decreased, the turn-on voltage instability reduced. The results suggest that water vapor related traps are strongly related to the instability of ZnO and HfZnO TFTs and that a proper combination of water vapor permeation barriers plays an important role in suppressing the device instability.