• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.6
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• pp.834-840
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• 2014

When the high speed train (KTX) departs from station in the high-speed line, intermittent on-board signal disappearance causes a hindrance of the operation punctuality. Therefore, we have a research objective to verify the causes of hindrance and to find an improvement plan. process of research, when train leaves the station, we applied sand on the rail to improve adhesive power, that sand has an effect on the ATC(Automatic Train Control) signal wave. We detected & analyzed signal waves which is came from detecting device by changing operation condition in accordance with sand material overage detection to be achieved.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.7
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.275-278
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• 2000

As the operating frequency of digital modules in network system becomes fast, integrity of signals between modules is regarded as a important factor in high speed system design. To guarantee the signal integrity, many factors that deteriorate quality of signal should be considered. In this paper, we survey many factors which be considered while in designing and imp]ementing the backplane for high speed router and analyze the simulation result and experimental result.

• 한국정보통신설비학회:학술대회논문집
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• 2006.08a
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• pp.57-61
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• 2006

As high speed internet users are tremendously increasing, three are keenly in need of development of high speed portable internet technology which can provide high quality wireless internet service cheaply even in the mobile. Unlike the FDD-CDMA, TDD-OFDMA has relatively poor wave environment with inducing interference, fading and delay because it agrees to multi-carrier modulation method and time-division radio telecommunication system. To solve this problem, it is necessary to develop repeater operating by digital signal processing method which have more strict wireless channel control and wave signal processing technology over TDD telecommunication equipments. This thesis is dealing with design and implementation of Digital RF Repeater which implemented 'Synchronization Acquisition Unit', 'TDD signal switching Unit', 'Feedback Signal Cancellation Unit'. Over this argument, we will develop digital RF repeater with more cheap, more adaptive in wave environment like oscillation control, adaptive wave monitoring and output increasing and having control function as a result it will be helpful for success in high speed portable internet service business.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2000.04a
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• pp.321-325
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• 2000

To obtain precise surface and high productivity, high speed end milling has been studied recently. Though high speed end milling is explicitly effective for precision surface generation geometrically, tool deflection, chatter vibration and frequency characteristics of end milling system deteriorate the theoretical surface. In this study, simulation algorithm and programming method are suggested to simulate machined surface using acceleration signal in high speed end milling. This simulation is conducted by considering vibrational effect of spindle system which was not considered by other researchers. Between simulated results and experiment results, good agreements were obtained.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.755-764
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• 2008

When the high speed train (KTX) departs from station in the high-speed line, sometimes on board signal disappears, which causes a hindrance of the operation punctuality, therefore, we have a research objective to verify the causes of hindrance and to find an improvement plan. In the process of research, when train left, we applied sand on the rail to improve adhesive power, whose sand has an effect on the ATC(Automatic Train Control) signal wave. We detected & analyzed signal waves which came from detecting device by changing operation condition in accordance with sand material

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.110-113
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• 2003

In this paper, the multi-channel high speed data acquisition system is implemented. This high speed signal processing system for 3-D image display is applicable to the manipulation of a medical image processing, multimedia data and various fields of digital image processing. In order to convert the analog signal into digital one, A/D conversion circuit is designed. PCI interface method is designed and implemented, which is capable of transmission a large amount of data to computer. In order to, especially, channel extendibility of images acquisition, bus communication method is selected. By using this bus method, we can interface each module effectively. In this paper, 32-channel A/D conversion and PCI interface system for 3-dimensional and real-time display of the retina image is developed. The 32-channel image acquisition system and high speed data transmission system developed in this paper is applicable to not only medical image processing as 3-D representation of retina image but also various fields of industrial image processing in which the multi-point realtime image acquisition system is needed.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.923-924
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• 2008

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.315-318
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• 1997

In terms of productivity, the speed of machining process has been increasing in most of engineering part. But the tapping process does not reach at enough level compared with other machining processes because of its complicate cutting mechanism. In the high speed tapping process, the one of important elements is tool monitoring system to prevent tool breakage. This paper describes tool monitoring system by acoustic emission(AE) in the tapping process. We used 2 types of AE sensors in this test. The one is commercial sensor which is used in other machining monitoring system like polishing and the other is a self-fabricated sensor for this test. In this test we purpose to find out the frequency of AE signal in tapping process and verify the possibility of applying AE sensor in in-process tapping monitoring system. Also grasp of characteristic of tapping process by AE signal is handled.

• Journal of Sensor Science and Technology
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• v.30 no.2
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• pp.82-87
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• 2021

In this paper, we propose a high-speed, low-power complementary metal-oxide semiconductor (CMOS) binary image sensor featuring a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector based on a double-tail comparator. The GBT photodetector forms a structure in which the floating gate (n+ polysilicon) and body of the PMOSFET are tied, and amplifies the photocurrent generated by incident light. The double-tail comparator compares the output signal of a pixel against a reference voltage and returns a binary signal, and it exhibits improved power consumption and processing speed compared with those of a conventional two-stage comparator. The proposed sensor has the advantages of a high signal processing speed and low power consumption. The proposed CMOS binary image sensor was designed and fabricated using a standard 0.18 ㎛ CMOS process.