• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.96-100
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• 2015

Adaptive background gain calibration loop for multi-lane serial links is proposed. In order to detect and cancel gain mismatches between lanes, a single digital loop using a ${\sum}{\Delta}$ ADC is employed, which provides a real-time adaptation of gain variations and is shared among all lanes to reduce power and area. Evaluation result showed that gain mismatches between lanes were well calibrated and tracked, resulting in timing budget at $10^{-6}$ BER increased from 0.261 UI to 0.363 UI with stable loop convergence.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.5 no.3
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• pp.164-168
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• 2012

LDPC decoder architectures are generally classified into serial, parallel and partially parallel architectures. Conventional method of LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation. This paper studies Horizontal Shuffle Scheduling (HSS) algorithm. In the result, number of iteration is half than conventional algorithm without performance degradation. Finally, this paper present design methodology of high-speed LDPC decoder and confirmed its throughput is up to about 600Mbps.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.7-10
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• 2004

This paper describes techniques to implement low-cost adapt ive Pipelined LMS filter for ASIC implement ions of high communication receivers. Power consumpiton can be reduced using a careful selection of architectural, algorithmic, and VLSI circuit techlifue A Pipelined architecture for the strength-reduced algorithm is then developed via the relaxed look-ahead transformation. This technique, which is an approximation of the conventional look-ahead compution, maintains the functionality of the algorithm rather than the input-output behavior Convergence maiysis of the Proposed architecture has been presented and support via simulation results. The resulting pipelined adaptive filter achives a higher though put requires lower power as compared to the filter using the serial algorithm.

• Journal of information and communication convergence engineering
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• v.1 no.4
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• pp.177-182
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• 2003

Conventional multilayer feedforward artificial neural networks are very effective in dealing with spatial problems. To deal with problems with time dependency, some kinds of memory have to be built in the processing algorithm. In this paper we show how the newly proposed Serial Input Neuron (SIN) convolutional decoders can be derived. As an example, we derive the SIN decoder for rate code with constraint length 3. The SIN is tested in Gaussian channel and the results are compared to the results of the optimal Viterbi decoder. A SIN approach to decode convolutional codes is presented. No supervision is required. The decoder lends itself to pleasing implementations in hardware and processing codes with high speed in a time. However, the speed of the current circuits may set limits to the codes used. With increasing speeds of the circuits in the future, the proposed technique may become a tempting choice for decoding convolutional coding with long constraint lengths.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3148-3150
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• 2000

Turbo codes that have attracted a great attention in recent years are applied to wireless communication networks that require variable quality of service and transmit over unknown fading channel. A MAP decoder is the constituent of turbo decoder. In this paper, we propose a high speed architecture of MAP decoder and a new normalization technique, In conclusion, this paper presents the efficient implementation of serial block MAP decoder for turbo codes.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.1
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• pp.69-74
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• 2010

Now the CAN(controller Area Network) is using electronic modules as a serial communication which is very robust to noise. Especially the CAN is using for automotive part that very popular in which automotive electronic control module, engine controller unit, sensor modules, etc. but the CAN has the order of priority to linking node and also has fault confinement so using in these features that is applied to in factory automation product line. The CAN communication is basically very robust to electric noise so varied applying to others part. In this paper, we suggest to CAN interface for embedded system that is possible for error detection using two CAN nodes on Hi-speed, full-CAN.

• Proceedings of the KSR Conference
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• 2010.06a
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• pp.1255-1261
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• 2010

An operating information and fault recode of train is very important information for safety driving and maintenance. And these information is increased and need high speed as the number of trains is increased. Wireless LAN or CDMA network is efficient to report more complicated and various information from vehicle to server in control center. Existing wireless transmission system has weakness due to transmission system is separated with TDCS and standalone. At first, standalone system needs space to be installed and cost is increased. And data transmission capacity and speed is limited by complicated structure that transmission system receive data thru serial communication like RS232 and then data transmission system send data to server in control center. This article is study to develop embedded & wireless fault code transmission device to be installed in TDCS to overcome weakness of space and to have more cost effective and simple structure. It is adapted 802.11b/g WiFi for wireless communication and OS is used embedded Linux that can easily implement wireless communication environment and ensure TCP/IP communication’s security. We also implement simple server to test wireless communication between embedded & wireless fault code transmission device and server in control center.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.2
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• pp.324-328
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• 2012

A recovered jitter of CDR(Clock and Data Recovery) Circuit based on Dual-loop DLL(Delay Locked Loop) for data recovery in high speed serial data communication is changed by depending on the input data and reference clock frequency. In this paper, 2-step DPC which has constant jitter performance for wide-range input frequency is proposed. The designed prototype 2-step CDR using proposed 2-step DPC has operation frequency between 200Mbps and 4Gbps. Average delay step of 2-step DPC is 10ps. Designed CDR circuit was tested with 0.18um CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2670-2674
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• 2010

FlexRay is a new standard of network communication system which provides a high speed serial communication, time triggered bus and fault tolerant communication between electronic devices for future automotive applications. The speed of FlexRay is 10 times higher than that of CAN. In this paper, FlexRay module is implemented using MC9S12XF512 micro-controller and gateway converting CAN message to FlexRay message. It is shown that the implemented system operates successfully.

• Journal of Institute of Control, Robotics and Systems
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• v.16 no.6
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• pp.546-552
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• 2010

As the demands for the safety and convenience applications of the vehicles increase, the data load for the In-vehicle Network has increased significantly. As a result, a deterministic and fault-tolerant communication system is required to implement the safety critical applications such as X-by-wire systems. FlexRay communication system is a new standard of network communication system which provides the high speed serial communication, time triggered bus and fault tolerant communication between electronic devices. In addition to time-triggered communication, as providing of the event-triggered communication such as CAN, FlexRay protocol is able to manage the restricted communication resource more effectively. This paper presents the development of FlexRay driver which will be applied to the future ECU's communication system. To develop the FlexRay driver, the FlexRay requirement specification and FlexRay specification is analyzed. The developed FlexRay driver is implemented by using MPC5567 microprocessor of the Freescale semiconductor. To verify the developed FlexRay driver, the waveform of the FlexRay driver was measured and compared with the CAN communication system. As a result, the bus load is reduced about 13% compared with the CAN communication system.