• 한국항공우주학회지
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• 제36권6호
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• pp.616-620
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• 2008

인공위성체에서의 데이터 처리유닛은 고 신뢰성을 갖추어야 하고 또한 최근 탑재체의 요구사항이 늘어나면서 고속으로 데이터를 처리할 수 있어야 한다. 이러한 고 신뢰도 및 고속데이터 처리유닛을 개발하려면 우주용 프로세서의 활용, 고속 데이터 인터페이스 기술 활용, 대용량 메모리 제어기술 활용 및 우주 방사선 환경에서 데이터를 유지하는 기술을 모두 응용하여야 한다. 또한 단위 기능블록으로 모듈화하고 기능 확장이 용이한 구조로 디자인하여 활용성을 높이고자 한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1029-1032
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• 1998

In this paper, a comparative study is presented to evaluate the addition architecture of the high-speed checksum module in TCP/IP processing. In order to speed up TCP/IP processing, H/W implementation offers concurrent and parallel processing to yield high speed computation, with respect to S/W implementation. This research aims at comparing two addition architectures of checksum module, which is the major botteleneck in TCP/IP processing. The 16-bit and 8-bit byte-by-byte addition architecture are implemented by the full custom design, and compared, in analytical and experimental manner, from standpoint of space and performance. For LG $0.6\mu\textrm{m}$ TLM process, the 8-bit addition implementation requires the area, 1.3 times larger than the 16-bit one, and it operates at 80MHz while the 16-bit one runs by 66MHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.373-374
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• 2008

This paper proposes an architecture for high-speed data processing of the DF-DPD. The DF-DPD have the architecture feedbacking the detected phase to reduce the noise of the previous symbol as phase reference. However, the feedback of the detected phase results in lower data processing speed than that of the conventional differential phase detection. In this paper, an architecture is proposed for high-speed data processing of the differential phase detectors with decision feedback in the DF-DPD.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.118.5-118
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• 2001

This paper describes an image processing method for inspecting the surface outlook of high speed moving plates. Noise free image and a new real time processing methods are required to inspect the surface outlook of the high speed moving plates in real time. It is difficult to get a noise free image due to a signal noise, a light noise and background image in typical industrial factory. Thus, pre-processing techniques should be required to get a good image and produce so many time steps to proceed the image data. The objective of this research is to get image on the surface of the moving plates with a speed of 1m/sec and to detect some defaults on the surface image. So, the pre-processing techniques ...

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 학술대회 논문집 정보 및 제어부문
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• pp.177-179
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• 2005

This paper suggests a high-speed blurred blob image inspection algorithm. When we inspect some products using high-resolution camera, the detected blob images usually have severe blur. And the blur makes it hard to detect an object. There are many blur-processing algorithms, but most of them have no real-time property for high-speed applications at all. In this paper, an MMX technology based algorithm is suggested. The suggested algorithm was found to be effective to detect the blurred blob images via many simulations and long time real-plant experiments.

• 전자공학회논문지B
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• 제31B권7호
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.449-452
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• 1998

In this study, the basic image-board and algorithm has been developed to extract a road lane by modeling the driving process. The high speed processing enables an image capture, processing and prompt decision making. In order to high speed processing ASIC like FPGA was designed and integrated in one board system. The algorithm enabling road driving must recognize a straight and bend edge separately. The high speed image processing board using FPGA can be used in real-time decision makeing system for road driving and in the machine vision under bad working environments like a coal mine. And it also can be used in the safety control system in subway and in image input system of CCTV and CATV by designing the board to meet various user's needs.

• 반도체디스플레이기술학회지
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• 제11권3호
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• pp.39-44
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• 2012

Electronics in modern lives have become more miniaturized and precise. Multi Layered Ceramic Capacitor (MLCC) occupies 50% of electronic components consisting of electronics. This high volume of the production needs high speed and more precise machine performances. The dominate parts of the production equipments are the module transporting components and the visual inspection module. Most visual inspection has been off-line because of the image processing time. In this paper, a new image processing method is proposed to reduce thousands of matrix calculation for image processing and realize on-line high speed inspection.

• 한국정보처리학회논문지
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• 제7권4호
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• pp.1263-1270
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• 2000

The operation frequency of High-speed Communication System becomes very fast with the advanced technology of VLSI chips and system implementation. There may exist various types of noise sources degrading the signal integrity in this system. The present main system is made of backplane, so faults can be brought whenever a board is removed, replaced or added. This backplane boards testing is a very important process to verify the operation of system. firstly, we model the effects of the internal noises in the High-speed Communication System to the signal line and propose a new design method to minimize these effects. For the design methodology, we derive the characterization value for each mode land them construct the optimal simulation model. We compare the result of own proposing method with that fo the existing methods, through simulation and show that the quality of High-speed Communication System is significantly enhanced. Secondary our proposing BIST for the Backplane Boards Testing is designed to guarantee that there is no fault in the high-speed communication system.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2009년도 춘계학술대회 논문집
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• pp.242-243
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• 2009

Friction stir welding and friction stir processing is a new solid state processing technique for ioining and micro..structural modification in metallic materials. It has been applied not only joining for light metals but also modification of the microstructure to enhance mechanical properties. In thin study, we investigated the mechanical properties for applied friction stir welding and processing under various parameters such as probe diameter, probe type, traveling speed and rotating speed for 5456-H116 AI allov. As a result of experiments, optimum condition of friction stir welding is traveling speed of 15mm/min, rotating speed of 500RPM at 6mm diameter probe. Moreover, in the case of friction stir processing, the optimum condition is traveling speed of 15mm/min, rotating speed of 250RPM at full screw probe. As above mentioned, the mechanical characteristics enhanced with the decreasing of traveling speed and the increasing of friction areas because of plastic flow due to high friction heat. These result can be used as reference data for ship repairment.