• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.29-29
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• 2000

This paper describes the design and implementation of a high-speed navigation computer to achieve precision navigation performance with Strapdown INS. The navigation computer inputs are velocity and angular increment data from the ISA at the signal of the 2404Hz interrupt and performs the removal of gyro block motion and the compensation of high dynamic errors at the 200Hz. For high-speed and high-accuracy, the computer consists of the 68040 micro-processor, 128k Memories, FPGAs, and so on. We show that the computer satisfies the required performance by In-Run navigation tests.

• 한국컴퓨터정보학회논문지
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• 제21권5호
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• pp.49-56
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• 2016

Increasing Internet traffic and forwarding table size need high performance IP address lookup engine which is a crucial function of routers. For finding the longest matching prefix, trie-based or its variant schemes have been widely researched in software-based IP lookup. As a software router, we enhance the IP address lookup engine using GPU which is a device widely used in high performance applications. We propose a data structure for multibit trie to exploit GPU hardware efficiently. Also, we devise a novel scheme that the root subtrie is loaded on Shared Memory which is specialized for fast access in GPU. Since the root subtrie is accessed on every IP address lookup, its fast access improves the lookup performance. By means of the performance evaluation, our implemented GPU-based lookup engine shows 17~23 times better performance than CPU-based engine. Also, the fast access technique for the root subtrie gives 10% more improvement.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.647-650
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• 1988

This paper proposes and sketches out a new parallel architecture of transputer-based pyramidal parallel array computer (TPPAC) used to process computationally intensive problems for geometric processing applications such as computer vision, image processing etc. It explores how efficiently the pyramid computer architecture is designed using transputer chips, and poses a new interconnection scheme for TPPAC without using additional transputers.

• 한국컴퓨터정보학회논문지
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• 제24권8호
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• pp.1-8
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• 2019

Modern computers provide tremendous computing capability and a large memory system. Hybrid memories consist of next generation memory devices and are adopted in high performance systems. However, the increased complexity of the microprocessor makes it difficult to operate the system effectively. In this paper, we propose a simple data migration method called Bandwidth-aware Data Migration (BDM) to efficiently use memory systems for high performance processors with hybrid memory. BDM monitors the status of applications running on the system using hardware performance monitoring tools and migrates the appropriate pages of selected applications to High Bandwidth Memory (HBM). BDM selects applications whose bandwidth usages are high and also evenly distributed among the threads. Experimental results show that BDM improves execution time by an average of 20% over baseline execution.

• 한국컴퓨터정보학회논문지
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• 제24권4호
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• pp.1-9
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• 2019

LRR(Loose Round Robin) warp scheduling policy for GPU architecture results in high warp-level parallelism and balanced loads across multiple warps. However, traditional LRR policy makes multiple warps execute long latency operations at the same time. In cases that no more warps to be issued under long latency, the throughput of GPUs may be degraded significantly. In this paper, we propose a new warp scheduling policy which utilizes latency hiding, leading to more utilized memory resources in high performance GPUs. The proposed warp scheduler prioritizes memory instruction based on GTO(Greedy Then Oldest) policy in order to provide reduced memory stalls. When no warps can execute memory instruction any more, the warp scheduler selects a warp for computation instruction by round robin manner. Furthermore, our proposed technique achieves high performance by using additional information about recently committed warps. According to our experimental results, our proposed technique improves GPU performance by 12.7% and 5.6% over LRR and GTO on average, respectively.

• 한국산업정보학회:학술대회논문집
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• 한국산업정보학회 2003년도 춘계학술대회
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• pp.3-7
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• 2003

For high performance Grid environments, an efficient GIS(Grid Information Service is required In the Metacomputing Directory Service(MDS) of the Glogus middleware, the Lightweight Directory Access Protocol(LDAP), which is a distributed directory service protocol, is used. The LDAP GIS differs from general purpose LDAP directories in that most of the LDAP operations are write in Grid environments. To get an efficient design of the GIS, it is thus required to analyze the performance of the LDAP system in the context of Grid environments. This paper presents the result of a performance analysis of LDAP systems. The main objective of the evaluation is to see the performance scalability of the LDAP system in the Grid environment where the write operations prevails. Based on these results, we suggest directions of an efficient LDAP-based GIS for a high performance Grid.

• Journal of Communications and Networks
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• 제17권4호
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• pp.370-383
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• 2015

Effective link quality estimation is a vital issue for reliable routing in wireless networks. This paper studies the performance of expected transmission count (ETX) under different traffic loads. Although ETX shows good performance under light load, its performance gets significantly worse when the traffic load is high. A broadcast packet storm due to new route discoveries severely affects the link ETX values under high traffic load, which makes it difficult to find a good path. This paper presents the design and implementation of a variation of ETX called high load - ETX (HETX), which reduces the impact of route request broadcast packets to link metric values under high load. We also propose a reliable routing protocol using link quality metrics, which is called link quality distance vector (LQDV). We conducted the evaluation of the performance of three metrics - HETX, ETX and minimum hop-count. The simulation results show that HETX improves the average route throughput by up to 25% over ETX under high traffic load. Minimum hop-count has poor performance compared with both HETX and ETX at all of the different traffic loads. Under light load, HETX and ETX show the same performance.

• Journal of Information Processing Systems
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• 제14권6호
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• pp.1398-1404
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• 2018

High-performance computing (HPC) provides to researchers a powerful ability to resolve problems with intensive computations, such as those in the math and medical fields. When an HPC platform is provided as a service, users may suffer from unexpected obstacles in developing and running applications due to restricted development environments and dependencies. In this context, operating system level virtualization can be a solution for HPC service to ensure lightweight virtualization and consistency in Dev-Ops environments. Therefore, this paper proposes three types of typical HPC structure for container environments built with HPC container and Docker. The three structures focus on smooth integration with existing HPC job framework, message passing interface (MPI). Lastly, the performance of the structures is analyzed with High Performance Linpack benchmark from the aspect of performance degradation in network communications under Docker.

• 한국멀티미디어학회논문지
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• 제8권12호
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• pp.1605-1612
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• 2005

This paper presents the knowledge and experience we obtained by employing multiprocessor systems as a computer simulation design verification to study high-performance computing system. This paper also describes a case study of symmetric multiprocessors (SMP) kernel on a 32 CPUs CC-NUMA architecture using an actual architecture. A small group of CPUs of CC-NUMA, high-performance computer system, is clustered into a processing node or cluster. By simulating the system design verification tools; we discussed SMP OS kernel on a CC-NUMA multiprocessor architecture performance which is $32\%$ of the total execution time and remote memory access latency is occupied $43\%$ of the OS time. In this paper, we demonstrated our simulation results for multiprocessor, high-performance computing system performance, using simulation-based design verification.

• Journal of Electrical Engineering and Technology
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• 제13권1호
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• pp.181-191
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• 2018

Rapid development of information technology makes our environment become smarter and massive high performance computers are providing powerful computing for that. Graphics Processing Unit (GPU) as a typical high performance component is being widely used for both graphics and general-purpose applications. Although it can greatly improve computing power, it also delivers significant power consumption and need sufficient power supplies. To make high performance computing more sustainable, the important step is to measure it. Current power technologies for GPU have some drawbacks, such as they are not applicable for power estimation at the early stage. In this article, we present a novel power technology to correlate power consumption and the characteristics at the programmer perspective, and then to estimate power consumption of source program without prerunning. We conduct experiments on Nvidia's GT740 platform; the results show that our power model is more accurately than regression model and has an average error of 2.34% and the maximum error of 9.65%.