• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.52-62
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• 2004

In this paper we look at the effect of Fringe-Enhanced-Barrier-lowering (FEBL) for high-K dielectric MOSFETs and the dependence of FEBL on various technological parameters (spacer dielectrics, overlap length, dielectric stack, S/D junction depth and dielectric thickness). We show that FEBL needs to be contained in order to maintain the performance advantage with scaled high-K dielectric MOSFETs. The degradation in high-K dielectric MOSFETs is also identified as due to the additional coupling between the drain-to-source that occurs through the gate insulator, when the gate dielectric constant is significantly higher than the silicon dielectric constant. The technology parameters required to minimize the coupling through the high-K dielectric are identified. It is also shown that gate dielectric stack with a low-K material as bottom layer (very thin $SiO_2$ or oxy-nitride) will be helpful in minimizing FEBL. The circuit performance issues with high-K MOS transistors are also analyzed in this paper. An optimum range of values for the dielectric constant has been identified from the delay and the energy dissipation point of view. The dependence of the optimum K for different technology generations has been discussed. Circuit models for the parasitic capacitances in high-K transistors, by incorporating the fringing effects, have been presented.

• Journal of IKEEE
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• v.25 no.1
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• pp.1-9
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• 2021

In this paper, a 4H-SiC UMOSFET was studied which is suitable for high voltage and high current applications. In general, SiO2 is a material most commonly used as a gate dielectric material in SiC MOSFETs. However, since the dielectric constant value is 2.5 times lower than 4H-SiC, it suffers a high electric field and has poor characteristics in the SiO2/SiC junction. Therefore, the static characteristics of a device with high-k material as a gate dielectric and a device with SiO2 were compared using TCAD simulation. The results show BV decreased, VTH decreased, gm increased, and Ron decreased. Especially when the temperature is 300K, the Ron of Al2O3 and HfO2 decreases by 66.29% and 69.49%. and at 600K, Ron decreases by 39.71% and 49.88%, respectively. Thus, Al2O3 and HfO2 are suitable as gate dielectric materials for high voltage SiC MOSFET.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.276-276
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• 2014

High-performance, fully-transparent, and top-gated oxide thin-film transistor (TFT) was successfully fabricated with Ta2O5 high-k gate dielectric on a glass substrate. Through a self-passivation with the gate dielectric and top electrode, the top-gated oxide TFT was not affected from H2O and O2 causing the electrical instability. Heat-treated InSnO (ITO) was used as the top and source/drain electrode with a low resistance and a transparent property in visible region. A InGaZnO (IGZO) thin-film was used as a active channel with a broad optical bandgap of 3.72 eV and transparent property. In addition, using a X-ray diffraction, amorphous phase of IGZO thin-film was observed until it was heat-treated at 500 oC. The fabricated device was demonstrated that an applied electric field efficiently controlled electron transfer in the IGZO active channel using the Ta2O5 gate dielectric. With the transparent ITO electrodes and IGZO active channel, the fabricated oxide TFT on a glass substrate showed optical transparency and high carrier mobility. These results expected that the top-gated oxide TFT with the high-k gate dielectric accelerates the realization of presence of fully-transparent electronics.

• Transactions on Electrical and Electronic Materials
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• v.10 no.4
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• pp.116-120
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• 2009

Ceramic-polymer composites have been investigated for their suitability as embedded capacitor materials because they combine the processing ability of polymers with the desired dielectric properties of ceramics. This paper discusses the dielectric properties of the ceramic ($BaTiO_3$)-polymer (Epoxy) composition as a function of ceramic particle size at a ceramic loading of 40 vol%. The dielectric constant of these ceramic-polymer composites increases as the powder size decreases. Results show that ceramic-polymer composites have a high dielectric constant associated with the $BaTiO_3$ powder with a 200 nm particle size, high insulation resistance, high breakdown voltage (> 22 KV/mm), and low dielectric loss (0.018-0.024) at 1 MHz.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1738-1745
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• 2015

Radiation characteristics of a probe-fed rectangular microstrip patch antenna printed on a finite grounded high permittivity substrate are investigated systematically for various square grounded dielectric substrate sizes with several thicknesses and dielectric constants by experiment and full wave simulation. The effect of the substrate size on the radiation characteristics of a rectangular patch antenna is mainly determined by the effective dielectric constant of surface waves on a grounded dielectric substrate. As the effective dielectric constant of surface waves increases, the substrate sizes for the maximum broadside gain and the required onset for a large magnitude of squint angle decrease, while the variations of the broadside gain, the front-to-back ratio, and the magnitude of squint angle versus the substrate size increase due to the increase of the power of the surface wave.

• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.5
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• pp.201-206
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• 2004

In order to investigate the optimum conditions for the effective ozone formation in a dielectric barrier discharge, measurements of ozone concentration were carried out for various conditions such as the gap length, the dielectric material and the operating gas. It was found that the optimum discharge conditions differed exceedingly in the types of operating gases and dielectric materials. In dry air, dielectric material with low dielectric constant and thermal conductivity, which might contribute to the restriction of the gas temperature rise in the discharge region, proved effective in obtaining both high ozone yield and concentration. The optimum gap length was considered to be in the range of 600-800 mm. In oxygen, using a quartz glass disk as a dielectric material, the required condition to obtain the high ozone yield and concentration was expanded.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.04a
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• pp.245-248
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• 1997

The dielectric resonators(DRs) with dielectric properties are widely used in microwave integrated circuit(MICs) and monolithic microwave integrated circuits(MMICS). The variational method as numerical simulation scheme would be applied to calculate the resonant frequencies(fr) and Q-factors of microwave dielectric resonators. The dielectric resonator with a cylindrical “puck” structure of high dielectric material is modeled in this simulation. The parameters, such as the diameter, the height, and the dielectric constant of dielectric resonator, would determine the resonant frequency and the Q-factor. The relationship between these parameters would effect each other to evaluate the approximate resonant frequency. This simulation method by the variational formula is very effective to calculate fr, and Q-factor. in high frequency microwave dielectric resonator The error rate of the simulation results and the measured results would be considered to design the microwave dielectric resonators.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.463-463
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• 2012

ITRS (international technology roadmap for semiconductors)에 따르면 MOS(metal-oxide-semiconductor)의 CD (critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/$SiO_2$를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두된다고 보고하고 있다. 일반적으로 high-k dielectric를 식각시 anisotropic 한 식각 형상을 형성시키기 위해서 plasma를 이용한 RIE (reactive ion etching)를 사용하고 있지만 PIDs (plasma induced damages)의 하나인 PIED (plasma induced edge damage)의 발생이 문제가 되고 있다. PIED의 원인으로 plasma의 direct interaction을 발생시켜 gate oxide의 edge에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 high-k dielectric의 식각공정에 HDP (high density plasma)의 ICP (inductively coupled plasma) source를 이용한 원자층 식각 장비를 사용하여 PIED를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. One-monolayer 식각을 위한 1 cycle의 원자층 식각은 총 4 steps으로 구성 되어 있다. 첫 번째 step은 Langmuir isotherm에 의하여 표면에 highly reactant atoms이나 molecules을 chemically adsorption을 시킨다. 두 번째 step은 purge 시킨다. 세 번째 step은 ion source를 이용하여 발생시킨 Ar low energetic beam으로 표면에 chemically adsorbed compounds를 desorption 시킨다. 네 번째 step은 purge 시킨다. 결과적으로 self limited 한 식각이 이루어짐을 볼 수 있었다. 실제 공정을 MOS의 high-k dielectric에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU (North Carolina State University) CVC model로 구한 EOT (equivalent oxide thickness)는 변화가 없으면서 mos parameter인 Ion/Ioff ratio의 증가를 볼 수 있었다. 그 원인으로 XPS (X-ray photoelectron spectroscopy)로 gate oxide의 atomic percentage의 분석 결과 식각 중 발생하는 gate oxide의 edge에 trap의 감소로 기인함을 확인할 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.543-548
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• 2014

In this paper, the dielectric relaxation and reliability of high capacitance density metal-insulator-metal (MIM) capacitors using $Al_2O_3-HfO_2-Al_2O_3$ and $SiO_2-HfO_2-SiO_2$ sandwiched structure under constant voltage stress (CVS) are characterized. These results indicate that although the multilayer MIM capacitor provides high capacitance density and low dissipation factor at room temperature, it induces greater dielectric relaxation level (in ppm). It is also shown that dielectric relaxation increases and leakage current decreases as functions of stress time under CVS, because of the charge trapping effect in the high-k dielectric.

• Journal of Sensor Science and Technology
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• v.29 no.1
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• pp.7-13
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• 2020

Dielectric capacitors are integral components in electronic devices that protect the electric circuit by providing modulated steady voltage. Explosive growth of the electric automobile market has resulted in an increasing demand for dielectric capacitors that can operate at temperatures as high as 400 ℃. To surpass the operation temperature limit of currently available commercial capacitors that operate in temperatures up to 125 ℃, Bi_1/2Na_1/2TiO₃ (BNT), which has a large temperature-insensitive dielectric response with a maximum dielectric permittivity temperature of 300 ℃, was selected. By introducing an intentional A-site cation deficiency and post-heat treatment, we successfully manage to control the dielectric properties of BNT to use it for high-temperature applications. The key feature of this new BNT is remarkable reduction in dielectric loss (0.36 to 0.018) at high temperature (300 ℃). Structural, dielectric, and electrical properties of this newly developed BNT were systematically investigated to understand the underlying mechanism.