• Journal of Power Electronics
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• v.16 no.1
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• pp.227-237
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• 2016

A novel digital current control strategy for digitally controlled DC-DC switching converters, referred to as Adjacent Cycle Sampling (ACS), is proposed in this paper. For the ACS current control strategy, the available time interval from sampling the current to updating the duty ratio, is approximately one switching cycle. In addition, it is independent of the duty ratio. As a result, the contradiction between the processing speed of the hardware and the transient response speed can be effectively relaxed by using the ACS current control strategy. For digitally controlled buck DC-DC switching converters with trailing-edge modulation, digital current control algorithms with the ACS control strategy are derived for three different control objectives. These objectives are the valley, average, and peak inductor currents. In addition, the sub-harmonic oscillations of the above current control algorithms are analyzed and eliminated by using the digital slope compensation (DSC) method. Experimental results based on a FPGA are given, which verify the theoretical analysis results very well. It can be concluded that the ACS control has a faster transient response speed than the time delay control, and that its requirements for hardware processing speed can be reduced when compared with the deadbeat control. Therefore, it promises to be one of the key technologies for high-frequency DC-DC switching converters.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.26-29
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• 2000

The conventional types of X-ray generators were bulky in physical size and heavy in weight and the control accuracies of the output voltages were not always satisfacotry. The high frequency switching inverter and converter technology on power conversion and control systems have been greatly closed up introducing power semiconducot devices. To decreasing the volume and the weight of high voltage transformer and to stabilize ripple. In this paper the newly developed x-ray generator in a low cost using duty modulation PWM inverter. This system verify improved performance by stabilize ripple of X-ray tube voltage and compared the reproducibility linearity and dose in single phase three phase and PSU.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.781-783
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• 1993

The GTO model is based on the Ebers-Moll equation extened to include the three-junction devices and a detailed description of the implementation of the model equation as well as defferent tests are discussed. Problems to be considered for the snubber design, such as voltage spike reduction, maximum GTO anode current, and switching power, were discussed using the calculation model. The macro model is very useful for simulation of GTO circuit and high power circuit switch in high frequency and complex structure.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.346-347
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• 2019

본 논문에서는 3.3 [kW] on-board charger (OBC) 용 phasw-shifted full-bridge (PSFB) 컨버터의 고효율 및 고전력 밀도 달성을 위한 스위칭 주파수 설계 방안을 제안한다. 스위칭 주파수에 따라 달라지는 손실 양상 및 전력 밀도에 대해 분석하기 위해 각 스위칭 주파수 별 반도체 소자 손실과 수동 소자 손실을 계산하고, 수동 소자의 부피 변화에 따른 전력밀도 변화를 분석한다. 분석 결과를 바탕으로 고효율 및 고전력밀도 달성을 위한 시스템 설계 포인트를 선정하고 시뮬레이션을 통하여 설계 결과를 검증한다.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.369-370
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• 2020

본 논문에서는 전기자동차용 양방향 배터리 충전장치에 사용되는 CHFL(Cycloconverter-type High Frequency Link) 컨버터에서 발생하는 고전압 스파이크 저감을 위한 스위칭 방법을 제안한다. CHFL 컨버터는 양극성 고주파 파형 정류시 LC 필터의 인덕터와 변압기의 누설 인덕터에 저장된 에너지로 인해 고전압 스파이크가 발생하게 된다. 제안된 스위칭 방법은 환류 구간을 통해 저장된 에너지를 회생시킴으로서 고전압 스파이크 문제를 해결할 수 있다. 제안된 스위칭 방법의 성능은 MATLAB/ Simulink 시뮬레이션을 통해 검증하였다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.16-24
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• 2002

This work describes a 10b 120 MSample/s CMOS pipelined A/D converter(ADC) based on a merged-capacitor switching(MCS) technique for high signal processing speed and high resolution. The proposed ADC adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area, and employs a MCS technique which improves sampling rate and resolution reducing the number of unit capacitor used in the multiplying digital-to-analog converter (MDAC). The proposed ADC is designed and implemented in a 0.25 um double-poly five-metal n-well CMOS technology. The measured differential and integral nonlinearities are within ${\pm}$0.40 LSB and ${\pm}$0.48 LSB, respectively. The prototype silicon exhibits the signal-to-noise-and-distortion ratio(SNDR) of 58 dB and 53 dB at 100 MSample/s and 120 MSample/s, respectively. The ADC maintains SNDR over 54 dB and the spurious-free dynamic range(SFDR) over 68 dB for input frequencies up to the Nyquist frequency at 100 MSample/s. The active chip area is 3.6 $mm^2$(＝ 1.8 mm ${\times}$ 2.0 mm) and the chip consumes 208 mW at 120 MSample/s.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.6
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• pp.57-65
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• 2007

This paper presents the design of single phase PFC(Power Factor Correction) using a DSP(TMS320F2812). In order to realize the proposed boost PFC converter in average current mode control, the DSP requires the A/D sampling values for a line input voltage, a inductor current, and the output voltage of the converter. Because of a FET switching noise, these sampling values contain a high frequency noise and switching ripple. The solution of A/D sampling keeps away from the switching point. Because the PWM duty is changed from 5% to 95%, we can#t decide a fixed sampling time. In this paper, the three A/D converters of the DSP are started using the prediction algorithm for the FET ON/OFF time at every sampling cycle(40 KHz). Implemented A/D sampling algorithm with only one timer of the DSP is very simple and gives the autostart of these A/D converters. From the experimental result, it was shown that the power factor was about 0.99 at wide input voltage, and the output ripple voltage was smaller than 5 Vpp at 80 Vdc output. Finally the parameters and gains of PI controllers are controlled by serial communication with Windows Xp based PC. Also it was shown that the implemented PFC converter can achieve the feasibility and the usefulness.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.2
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• pp.476-484
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• 2010

Recently, as the piezoelectric transformer technology develops, piezoelectric transformer may become a variable alternative to magnetic transformers in various applications. Because it was have to favorable characteristics such as electromagnetic-noise free, compact size, higher efficiency, and superior power density, linkage flux, noiseless, etc. its resonance frequency was used to output waveform of a sine wave. In this paper, the switching mode power supply of about 87.2[KHz] is driven by the multilayer thickness vibration mode piezoelectric transformer and the DC to DC converter drive circuit using an electrical equivalent circuit is proposed. Also, it was possible to drive power source device of the high-luminance LED by propose circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.1-8
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• 2012

This paper presents a fully-integrated buck converter equipped with packaging inductors. These inductors include parasitic inductances of the bonding wires and lead frames in the package. They have significantly better Q factors than the best on-chip inductors implemented on silicon. This paper also proposes a low-swing gate driver for efficient regulation of high-frequency switching converters. The low-swing driver uses the voltage drop of a diode-connect transistor. The proposed converter is designed and fabricated using a $0.13-{\mu}m$ CMOS process. The fully-integrated buck converter achieves 68.7% and 86.6% efficiency for 3.3 V/2.0 V and 2.8 V/2.3 V conversions, respectively.

• Journal of the Korean Society for Railway
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• v.20 no.3
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• pp.329-338
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• 2017

A recent trend of technical development in auxiliary-power-supplies (APS) is to replace 60Hz low frequency transformers with isolated type dc/dc converters. This paper introduces the technical trend in APS structures and proposes a power converter circuit suitable for high-efficient and light-weight APS. By utilizing the resonant converter, which achieves ZCS, to reduce switching losses, various types of APS structures (1-stage and 2-stage) are reviewed, and they are verified by simulation. The full-bridge resonant LLC converter is designed with a 1-stage power converting structure; the resonant converter topology is designed with a 2-stage power converting structure that has a pre-regulator converter to compensate for the wide input voltage range. Both a step-down converter and a step-up converter are designed and compared for the pre-regulator in the 2-stage structure. Operational characteristics are compared with simulation results and loss analyses are presented to proposes appropriate system structure and topologies.