• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.68-75
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• 2009

In this paper, an efficient proposed CDR(Clock and Data Recovery Circuits) using 1/4-rate clock based on dual-interpolator is proposed. The CDR is aimed to overcome problems that using multi-phase clock to decrease the clock generator frequency causes side effects such as the increased power dissipation and hardware complexity, especially when the number of channels is high. To solve these problems, each recovery part generates needed additional clocks using only inverters, but not flip-flops while maintaining the number of clocks supplied from a clock generator the same as 1/2-rate clock method. Thus, the reduction of a clock generator frequency using 1/4-rate clocking helps relax the speed limitation and power dissipation when higher data rate transfer is demanded.

• Journal of the Korea Concrete Institute
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• v.22 no.6
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• pp.817-824
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• 2010

The concrete containment structures have been widely used in nuclear power plants, LNG storage tanks, etc., due to their high safety and economic efficiency. The containment structure consists of a bottom slab, wall, ring beam and dome. The shape of the roof dome has a very significant effect on structural safety, the quantity of materials, and constructability; the thickness and curvature of the dome should therefore be determined to give the optimum design. The ring beam plays the role as supports for the dome, resulting in a minimized deformation of the wall. The main issues in designing the ring beam are the correct dimensions of the section and the prestress level. In this study, an efficient design procedure is proposed that can be used to determine an optimal shape and prestress level of the dome and ring beam. In the preliminary design stage of the procedure, the membrane theory of shells of revolution is adopted to determine several plausible alternatives which can be obtained even by hand calculation. Based on the proposed procedures, domes and ring beams of the existing domestic containment structures are analyzed and some improvements are discussed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.198-204
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• 2001

In this paper, a 3V 8-bit 200MSPS CMOS folding / interpolation A/D Converter is proposed. It employs an efficient architecture whose FR(Folding Rate) is 8, NFB(Number of Folding Block) is 4, and IR (Interpolating Rate) is 8. For the purpose of improved SNDR by to be low input frequency, distributed track and hold circuits are included. In order to obtain a high speed and low power operation, further, a novel dynamic latch and digital encoder based on a novel delay error correction are proposed. The chip has been fabricated with a 0.35${\mu}{\textrm}{m}$ 2-poly 3-metal n-well CMOS technology. The effective chip area is 1070${\mu}{\textrm}{m}$$\times$650${\mu}{\textrm}{m}$ and it dissipates about 230mW at 3.3V power supply. The INL is within $\pm$1LSB and DNL is within $\pm$1LSB, respectively. The SNDR is about 43㏈, when the input frequency is 10MHz at 200MHz clock frequency.

• The KIPS Transactions:PartC
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• v.11C no.6 s.95
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• pp.747-754
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• 2004

Today, wireless LANs are widely deployed in various places such as corporate office conference rooms, industrial warehouses, Internet-ready classrooms, etc. However, new concerns have been raised regarding suity. Currently, both virtual private network(VPN) and WEP are used together as a strong authentication mechanism. While security is increased by using VPN and WEP together, unnecessary redundancy occurs causing power consumption increase and authentication speed decrease in the authentication process. In this paper a new synchronization protocol for authentication is proposed which allows simple authentication, minimal power consumption at the mobile station, and high utilization of authentication stream. This is achieved by using one bit per a frame authentication, while main authentication process including synchronization is handled by access points. Computer simulation reveals that the proposed scheme significantly improves the authentication efficiency in terms of the number of authenticated frames and authentication speed compared with an earlier protocol employing a similar authentication approach.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.36-36
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• 2010

Currently, there are several newly developed energy resources for the future to replace petroleum resources such as hydrogen fuel cell, solar cell, wind power, and etc. Among them, solar cell has attracted a worldwide concern, because it has an enormous amount of resources. In general, a study of solar cells can be classified in to an area of bulk type and thin-film type. Inorganic solar cells based on silicon have been tremendously developed in technology and efficiency. However, since there are many lithographic steps, high processing temperature approximately $1000^{\circ}C$, and expensive raw materials, a manufacturing cost of device are nearly reaching a limit. Contrary to those disadvantages, organic solar cells can be manufactured at room temperature. Also, it has many advantages such as a low cost, easy fabrication of thin film, and possible manufacture to a large size. Because it can be made to be flexible, research and development on solar cells are actively in progress for the next generation. ever though an efficiency of the organic solar cell is low compared to that of inorganic one, a continuous study is needed. In this paper, we report optimal device structure obtained by a program simulation for design and development of highly efficient organic photovoltaic cells. we have also compared simulated results to experimental ones.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.6
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• pp.9-16
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• 2011

Due to the development and proliferation of ubiquitous technologies and services, various sensor network applications are being appeared on the stage. The needs for algorithms requiring sensor data fusion and complex signal processing with a high-performance processor such as a digital signal processor are also increased. However, it is difficult to use such processor for the low-power sensor network operating with a battery because of power consumption. This paper proposes a hybrid-type sensor module architecture supporting wakeup/sleep software framework for the wireless sensor node and shows the implemented sensor node platform and performances focused on the energy consumption and wakeup time.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.9
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• pp.27-34
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• 2011

Cognitive Radio, which is proposed to improve the efficiency of wireless communication systems is the system to share primary user's frequency bands with a secondary user. In this situation, a secondary user uses NC-OFDM (Non-contiguous Orthogonal Frequency Division Multiplexing) to transmit data effectively without interfering with the primary user's spectrum. However, NC-OFDM, in common with contiguous OFDM, degrades the performance of the system by generating high PAPR (Peak-to-Average Power Ratio). In this paper, firstly, we analyse PAPR corresponding to the distribution of subcarriers in NC-OFDM. Then the PAPR reductions that employ the PTS (Partial Transmit Sequence) and SLM (Selective Mapping) are evaluated. Finally, the computational complexities of the PTS and SLM adopting pruned-FFT are compared with conventional PTS and SLM. Further, it is shown that the NC-OFDM with pruned-FFT is more efficient than the contiguous OFDM in terms of computational complexity and PAPR reduction performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.760-770
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• 2016

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.478.1-478.1
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• 2014

We investigated $MoO_3$ graded ITO electrodes for organic solar cells (OSCs) without PEDOT:PSS buffer layer. The effect of $MoO_3$ thickness on the electrical, optical, and structural properties of $MoO_3$ graded ITO anodes prepared by RF/DC magnetron co-sputtering system using $MoO_3$ and ITO targets was investigated. At optimized conditions, we obtained $MoO_3$ graded ITO electrodes with a low sheet resistance of 13 Ohm/square, a high optical transmittance of 83% and a work function of 4.92 eV, comparable to conventional ITO films. Due to the existence of $MoO_3$ on the ITO electrodes, OSCs fabricated on $MoO_3$ graded ITO electrode without buffer layer successfully operated. Although OSCs fabricated on ITO anode without buffer layer showed a low power conversion efficiency of 1.249%, OSCs fabricated on $MoO_3$ graded ITO electrode without buffer layer showed a outstanding cell performance of 2.545%. OSCs fabricated on the $MoO_3$ graded ITO electrodes exhibited a fill factor of 61.275%, a short circuit current of 7.439 mA/cm2, an open circuit voltage of 0.554 V, and a power conversion efficiency of 2.545%. Therefore, $MoO_3$ graded ITO electrodes can be considered a promising transparent electrode for cost efficient and reliable OSCs because it could eliminate the use of acidic PEDOT:PSS buffer layer.

• Journal of Engineering Education Research
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• v.13 no.3
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• pp.11-17
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• 2010

Korea plans to be the world's first country to transform its electricity network into "smart grids," which use information and operational technologies to help to facilitate the reduction of carbon emissions, make more efficient use of existing infrastructure/resources through meeting customer demand/less generation, and support renewable resources with real time monitoring and controls. In this situation, universities do the needful on priority to nurture smart grid engineers who will be responsible for state-of-the-art technologies as today's electric grid transitions to a digital network. This paper thus attempts to permanently turn out high-quality human resources in electrical engineering by fleshing out strategies for training smart electric grid engineers, based on lessons from a national undertaking of nurturing qualified power IT engineers starting on February 1 of 2007.