• 한국철도학회:학술대회논문집
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• 한국철도학회 2008년도 춘계학술대회 논문집
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• pp.2021-2026
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• 2008

Recently, a high speed rail consists of many train coaches and power cars. For keeping the reliable train communication system with train coaches and power cars, train uses the OSI model(Open Systems Interconnection Basic Reference Model) and KTX(Korea Train eXpress) only uses the Physical to Transport layer of OSI model. This paper describes the analysis of CLNP(Connectionless Network Protocol) and ES-IS(End System to Intermediate System) protocols used in KTX for the network layer. CLNP is used to send data to other system and ES-IS protocol is used to route and send information between end systems and intermediate systems. Also this paper presents the protocol parsing program and implementation of Network layer.

• 한국컴퓨터정보학회논문지
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• 제4권4호
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• pp.94-100
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• 1999

본 논문은 흡필드 모델의 실수연산을 고속으로 수행할 수 있는 디지털 신경회로망의 구현에 관한 연구이다. 흡필드 모델［1］-［8］의 연산과정은 행렬-벡터의 연산으로 기술 할 수 있으며, 이 연산과정은 순환, 반복적으로 이루어지므로 어레이프로세서 구조로 설계하기에 적합하다. 또한, Look-up-Table(연산표)에 의하여 비선형 함수를 출력함으로써, 고속의 실수 연산을 수행할 수 있도록 설계하였다. 본 논문에서 제안한 방법은 현재 개발된 VLSI기술로 실현 가능하기 때문에 실제 신경회로망의 응용분야에 이용될 수 있을 것으로 기대된다.

• 한국통신학회논문지
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• 제21권9호
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• pp.2415-2421
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• 1996

본 논문에서는 고속 통신망에서의 멀티캐스트를 위한 고속 수송 프로토콜 XTP(Xpress Transport Protocol) Rev 4.0 을 Windows NT 상에 구현하고 그 성능을 평가하였다. 프로토콜은 이벤트(Event) 구동 방식으로 설계되었으며, 성능향상을 위해 커널 내부에 네트워크 드라이버의 형태로 구현하였다. 구현된 프로토콜의 기능은 LAN 환경하에서 Windows NT 응용 프로그램들로 테스트되었으며, TCP와 성능비교를 수행하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 D
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• pp.2112-2114
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• 2003

In this paper, We used FPGA which was high speed counter implementation. It was Counting accurately rather fast so that there were we as a counter facility of the pulse implemented. We constructed wide environment rather because we used H8/3672 with FPGA. This FPGA was sythesized by A54SX72A. FPGA programmed by VHDL for a 208pin PQFP package. The measurement the pulse is possible though it peels off a maximum 200kHz. There is used at a stopping action movement and control of the body.

• 대한원격탐사학회:학술대회논문집
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• 대한원격탐사학회 2007년도 Proceedings of ISRS 2007
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• pp.537-539
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• 2007

Telemetry processing system requires minimum bit transition level in data streams to maintain a bit synchronization while receiving telemetry signal. PN code has a capability of providing the bit transition and is widely used in the packet communication of CCSDS. CCSDS PN code that generator polynomial is $h(x)=x^{8}+x^{7}+x^{5}+x^{3}+1$, and the random bit sequence that is generated from this polynomial is repeated with the cycle of 255 bits. As the resolution of satellite image increases, the size and transmission rate of data increases. To process of huge and bulky size of satellite image, the speed of CCSDS PN Processing is very important. This paper introduces the way of improving the CCSDS PN Processing speed through processing 128 bits at one time using the feature of cyclic structure that repeats after first 255 bytes by grouping the random bit sequence with 1 byte and Intel Streaming SIMD Extensions 2. And this paper includes the comparison data of processing speed between SSE2-applied implementation and not-applied implementation, in addition, the measured value of speed improvement.

• 시스템엔지니어링학술지
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• 제15권2호
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• pp.1-8
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• 2019

Autonomous vehicles operated in the rough terrain environment must satisfy various technical requirements in order to improve the speed. Therefore, in order to design and implement a technical architecture that satisfies the requirements for speed improvement of autonomous vehicles, it is necessary to consider the overall technology of hardware and software to be mounted. In this study, the technical architecture of the autonomous vehicle operating in the rough terrain environment is presented. In order to realize high speed driving in pavement driving environment and other environment, it should be designed to improve the fast and accurate recognition performance and collect high quality database. and it should be determined the correct running speed from the running ability analysis and the frictional force estimation on the running road. We also improved synchronization performance by providing precise navigation information(time) to each hardware and software.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 D
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• pp.2628-2630
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• 2002

This paper describes the design and implementation of the OFDM Modem using FPGA. The proposed OFDM method is based on IEEE 802.11a high-speed wireless LAN standard. The proposed and designed Pipeline FFT processor adopt the Radix-$2^2$SDF scheme. This method has a simple architecture and highly increases the calculation speed. And also it decreases the required number of registers. Therefore the proposed OFDM Modem reduces hardware size and improves the calculation speed. The OFDM Modem is implemented using $FLEX^{TM}$ FPGA.

• 전자공학회논문지B
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• 제31B권6호
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• pp.104-110
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• 1994

We proposed a high speed feature extraction algorithm and developed a feature vector extraction chip for high speed character recognition. It is hard to implement a high speed OCR by software alone with statistical method . Thus, the whole recognition process is divided into functional steps, then pipeline processed so that high speed processing is possible with temporal parallelism of the steps. In this paper we discuss the feature extraction step of the functional steps. To extract feature vector, a character image is normalized to 40$\times$40 pixels. Then, it is divided into 5$\times$5 subregions and 4x4 subregions to construct 41 overlapped subregions(10x10 pixels). It requires to execute more than 500 commands to extract a feature vector of a subregion by software. The proposed algorithm, however, requires only 10 cycles since it can extract a feature vector of a columm of subregion in one cycle with array structure. Thus, it is possible to process 12.000 characters per second with the proposed algorithm. The chip is implemented using EPLD and the effectiveness is proved by developing an OCR using it.

• Journal of Power Electronics
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• 제2권2호
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• pp.146-153
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• 2002

this paper presents an implementation of digital control system of speed sensorless for Reluctance Synchronous Motor (RSM) drives with direct torque control (DTC). The problem of DTC for high-dynamic performance RSM drive is generating a nonlinear torque due to a saturated nonlinear inductance curve with various load currents. The control system consists of stator flux observer, compensating inductance look-up table, rotor position/speed/torque estimator, two hysteresis band controllers, an optimal switching look-up table, IGBT voltage source unverter, and TMS320C31 DSP controller. The stator flux observer is based on the combined voltage and current model with stator flux feedback adapitve control that inputs are the compensated inductances, current and voltage sensing of motor terminal with estimated rotor angle for wide speed range. The rotor position is estimated rotor speed is determined by differentiation of the rotor position used only in the current model part of the flux observer for a low speed operation area. It does not requrie the knowledge of any montor paramenters, nor particular care for moter starting, In order to prove the suggested control algorithm, we have simulation and testing at actual experimental system. The developed sensorless control system is showing a good speed control response characterisitic result and high performance features in 20/1500 rpm with 1.0Kw RSM having 2.57 ratio of d/q reluctance.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(1)
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• pp.205-208
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• 2000

In this paper, we design Tracking Filter that is principal component of Frequency Hopping System. This filter can acquire hopping pattern in short time and track it at high speed. This is high Q, narrowband, RF filter whose center frequency is controlled digitally between 30MHz ∼ 88MHz.