• Proceedings of the KSR Conference
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• 2007.05a
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• pp.824-828
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• 2007

With increasing interest in the reduction of cost for operation and maintenance of overhead catenary system, various methods of condition monitoring have been developed and used in with high-speed analysis and advanced image processing techniques. This study utilizes a high-speed camera as inspecting system to measure the wear, stagger, hight and arc extinguishing test of overhead catenary system. All measuring image were captured by a high speed CMOS camera with PCI express output, which can acquire up to 1000 frames per second with the resolution 1024 × 1280 pixels. Line type laser source with a power equal to 300 mW and the National Instrument LabVIEW (8.0) based on vision acquisition software have been used in application programming interface for image acquisition, display, and storage. The proposed high-speed camera system is finally applied to measure the overhead catenary system showing promising on-field applications

• 한국정보통신설비학회:학술대회논문집
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• 2006.08a
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• pp.87-90
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• 2006

Nowadays, we can enjoy access to high speed network and advanced services of convergence between broadcasting and communication anywhere and anytime through a ubiquitous computing. So, now digital convergence devices come out constantly. These devices are required faster network environment for high speed data processing than before. In this paper, we describe the design of InfiniBnad network adapter, which is included two FPGA chipsets. When this adapter is installed to Digital Convergence Platform (DCP) network performance will be improved. The adapter includes 12channel serial ports for external communication and internally, uses PCI-Express bus. We have finished the test of high speed serial based network adapter through composing complete InfiniBand network and applied fabric management software. So, we have verified that it can be applied on DCP environment.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.220-223
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• 2012

Generally, SAW device, which uses Time Domain Sampling, requires high speed AD converter because SAW device (TDS) needs high sampling speed as much as its high data speed. However, the high price of AD converter discourages makers from using it. On the other hand, SAW device, which uses Frequency Domain Sampling, does not required high speed AD converter because SAW device (FDS) does not need high sampling speed. It is very efficient in price comparison to its performance because high processing speed of SAW device (FDS) can be implemented using low price Embedded Systems. The purpose of the thesis is to solve the issues above by designing and realizing SAW device (FDS) using SAW sensor for TDS.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.312-315
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• 2012

Generally, SAW device, which uses Time Domain Sampling, requires high speed AD converter because SAW device (TDS) needs high sampling speed as much as its high data speed. However, the high price of AD converter discourages makers from using it. On the other hand, SAW device, which uses Frequency Domain Sampling, does not required high speed AD converter because SAW device (FDS) does not need high sampling speed. It is very efficient in price comparison to its performance because high processing speed of SAW device (FDS) can be implemented using low price Embedded Systems. The purpose of the thesis is to solve the issues above by designing and realizing SAW device (FDS) using SAW sensor for TDS.

• Journal of electromagnetic engineering and science
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• v.6 no.3
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• pp.147-154
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• 2006

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de) interleaving and iterative decoding in a conventional maximum a posteriori(MAP) turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is come from the combination of the radix-4, dual-path processing, parallel decoding, and rearly-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit-error rate(BER) performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. Fixed on the parameters of N=212, iteration=3, 8-states, 3 iterations, and QPSK modulation scheme, we designed the adaptive high-speed turbo decoder using the Xilinx chip (VIRTEX2P (XC2VP30-5FG676)) with the speed of 17.78 Mb/s. From the results, we confirmed that the decoding speed of the proposed decoder is faster than conventional algorithms by 8 times.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.239-242
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• 1999

In this paper, we report the process/device design of high-speed, high-voltage SOI smart power IC for mobile communication system, high-speed HDD system and the electronic control system of automobiles. The high voltage LDMOS with 70V breakdown voltage under 0.8${\mu}{\textrm}{m}$ design rule, the high voltage bipolar with 40V breakdown voltage for analog signal processing, the high speed bipolar with cut-off frequency over 20㎓ and LDD NMOS for high density were proposed and simulated on a single chip by the simulator DIOS and DESSIS. And we extracted the process/device parameters of the simulated devices.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2861-2873
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• 1997

An FPU(Floating Point unit) is the principle component in high performance computer and is placed on a chip together with main processing unit recently. As a Processing speed of the FPU is accelerated, the rounding stage, which occupies one of the floating point Processing steps for floating point operations, has a considerable effect on overall floating point operations. In this paper, by studying and analyzing the processing flows of the conventional floating point adder/subtractor, multipler and divider, which are main component of the FPU, efficient rounding mechanisms are presented. Proposed mechanisms do not require any additional execution time and any high speed adder for rounding operation. Thus, performance improvement and cost-effective design can be achieved by this approach.

• Journal of Advanced Marine Engineering and Technology
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• v.20 no.3
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• pp.121-130
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• 1996

Permanent magnet synchronous motor is widely used in industrial drive applications due to high efficiency, high power ratio, and easy maintenance. Position and speed detectors required in this motor increase the drive cost, and reduce the application range. Some papers present the speed control without position and speed detectors using DSP characterized by high processing performance. However, DSP increases the cost, and makes the inplementation difficult. This study has performed the speed control without position and speed detector by means of the microprocessor system which can be easily accessed. The results of simulation and experiment showed comparatively good dynamics in spite of the sensorless system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.702-708
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• 2000

In this paper, we designed one-dimensional VLSI array with optimal pipeline period for high speed processing fractal image compression. The algorithm is derived which is suitable for VLSI array from axed block partition algorithm. Also the algorithm satisfies high quality of image and high compression-ratio. The designed VLSI array has optimal pipeline relied because the required processing time of PEs is distributed as same as possible. As this result, we can improve the processing speed up to about 3 times. The number of input/output pins can be reduced by sharing the input/output and arithmetic unit of the domain blocks and the range blocks.

• Proceedings of the Korean Society of Laser Processing Conference
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• 2006.11a
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• pp.128-132
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• 2006

Low-k wafer engraving process has been investigated by using UV pico-second laser with high repetition rate. Wavelength and repetition rate of laser used in this study are 355nm and 80MHz, respectively. Main parameters of low-k wafer engraving processes are laser power, work speed, assist gas flow rate, and protective coating to eliminate debris. Results show that engraving qualities of low-k layer by using UV pico-second pulse width and high repetition rate had better kerf edge and higher work speed, compared to one by conventional laser with nano-second pulse width and low repetition rate in the range of kHz. Assist gas and protective coating to eliminate debris gave effects on the quality of engraving edge. Total engraving width and depth are obtained less than $20{\mu}m$ and $10{\mu}m$ at more than 500mm/sec work speed, respectively. We believe that engraving method by using UV pico-second laser with high repetition rate is useful one to give high work speed of laser material process.