• 한국전자통신학회논문지
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• 제17권2호
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• pp.351-356
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• 2022

The parity function can be implemented with XOR (exclusive-OR) and XNOR (exclusive NOR) circuit. In this paper we propose a high performance XOR-XNOR circuit. The proposed circuitreduced the internal load capacitance on critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit presents the improved characteristics in average propagation delay time, power dissipation, power-delay product (PDP), and energy-delay-product (EDP). The proposed circuits are implemented with standard CMOS 0.18um technology. Computer simulations using SPICE show that the proposed circuit realizes the expected logic functions and achieves a reasonable performance.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권2호
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• pp.162-167
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• 2012

This paper describes the design of a high-performance unified SVM classifier circuit. The proposed circuit supports both linear and non-linear SVM classifications. In order to ensure efficient classification, a 48x96 or 64x64 sliding window with 20 window strides is used. We reduced the circuit size by sharing most of the resources required for both types of classification. We described the proposed unified SVM classifier circuit using the Verilog HDL and synthesized the gate-level circuit using 65nm standard cell library. The synthesized circuit consists of 661,261 gates, operates at the maximum operating frequency of 152 MHz and processes up to 33.8 640x480 image frames per second.

• Journal of Electrical Engineering and Technology
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• 제9권4호
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• pp.1332-1342
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• 2014

This paper proposes a novel test circuit for SiC transistors. On-state resistance under practical application conditions is an important characteristic for the device reliability and conduction efficiency of SiC transistors. In order to measure the on-state resistance in practical applications, high voltage is needed, and high current is also necessary to ignite performance for the devices. A soft-switching circuit based on synchronous buck topology is developed in this paper. To provide high-voltage and high-current stresses for the devices without additional spikes and oscillations, a resonant circuit has been introduced. Using the novel circuit technology, soft-switching can be successfully realized for all the switches. Furthermore, in order to achieve accurate measurement of on-state resistance under switching operations, an active clamp circuit is employed. Operation principle and design analysis of the circuit are discussed. The dynamic measurement method is illustrated in detail. Simulation and experiments were carried out to verify the feasibility of the circuit. A special test circuit has been developed and built. Experimental results confirm that the proposed circuit gives a good insight of the devices performance in real applications.

• 전자공학회논문지B
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• 제30B권11호
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• pp.1-10
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• 1993

This paper proposes a High Performance Full-Swing BiCMOS (HiF-BiCMOS) circuit which improves on the conventional BiCMOS circuit. The HiF-BiCMOS circuit has all the merits of the conventional BiCMOS circuit and can realize full-swing logic operation. Especially, the speed of full-swing logic operation is much faster than that of conventional full-swing BiCMOS circuit. And the number of transistors added in the HiF-BiCMOS for full-swing logic operation is constant regardless of the number of logic gate inputs. The HiF-BiCMOS circui has high stability to variation of environment factors such as temperature. Also, it has a preamorphized Si layer was changed into the perfect crystal Si after the RTA. Remarkable scalability for power supply voltage according to the development of VLSI technology. The power dissipation of HiF-BiCMOS is very small and hardly increases about a large fanout. Though the Spice simulation, the validity of the proposed circuit design is proved.

• Journal of Electrical Engineering and Technology
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• 제7권5호
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• pp.778-783
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• 2012

The synthetic short-circuit making test to adequately stress the circuit breaker has been specified as the mandatory test duty in the IEC 62271-100. The purpose of this test is to give the maximum pre-arcing energy during making operation. And this requires the making operation with symmetrical short-circuit current that is established when the breakdown between contact gap occurs near the crest of the applied voltage. Also, if the interrupting chamber of circuit breakers is designed as the type of common enclosure or the operation is made by the gang operated mechanism that three-phase contacts are operated by one common mechanism, three-phase synthetic making test is basically required. Therefore, several testing laboratories have developed and proposed their own test circuits to properly evaluate the breaker performance. With these technical backgrounds, we have developed the new alternative three-phase making circuit.

• 한국소프트웨어감정평가학회 논문지
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• 제15권1호
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• pp.103-107
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• 2019

최근 저전력 고속 디지털 데이터 통신을 구현 하기위해 많은 기술들이 개발되고 있는 추세이며 듀티사이클 보정에 관련된 기술도 그중 하나이다. 본 논문에서는 전압제어 링 발전기용 저-면적 듀티사이클 보정 회로를 제안하였다. 듀티사이클 보정 회로는 전압제어 링 발진기의 180도 위상차이를 이용하여 듀티사이클을 보정하는 회로이며, 제안된 저-면적 듀티사이클 회로는 기존의 플립플롭을 TSPC(True Single Phase Clocking) 플립플롭으로 변경하여 회로를 구성하였고 이로 인하여 저-면적 고성능 회로를 구현하였다. 일반적인 플립플롭을 대신하여 TSPC플립플롭을 사용하여 기존 회로 대비 저-면적으로 회로 구현이 가능하며 고속 동작에 용이하여 저-전력용 고성능 회로에 활용될 것으로 기대된다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(2)
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• pp.839-841
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• 2004

This paper presents a SPMSM servo motor drive system using high performance TMS320 F281T DSP for the industrial application. This high performance DSP contains some special peripheral circuits such as PWM (Pulse Width Modulation) waveform generation circuit, Quadrature Encoder Pulse (QEP) generation circuit and Analog to Digital Converter (ADC) circuit. In this paper, a servo drive control system is constructed using high performance DPS for the overall system cost reduction and the size minimization.

• Nuclear Engineering and Technology
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• 제56권6호
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• pp.2395-2403
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• 2024

With the rapid development of DC high voltage accelerator, higher requirements have been raised for the design of DC high voltage power supply, requiring more stable high voltage with lower output ripple. Therefore, it also puts forward higher requirements for the parameter design of the voltage doubling rectifier circuit, which is the core component of the DC high voltage power supply. In order to obtain output voltage with better performance, the effects of the working frequency, the stage capacitance and the load resistance on the output voltage of the voltage doubling rectifier circuit are studied in detail by simulation. It can be concluded that the higher the working frequency of the transformer, the larger the stage capacitance, the larger the load resistance and the better the output voltage performance in a certain range. Based on this, a 2.5 MV voltage doubling rectifier circuit driven by a 120 kHz frequency transformer is designed, developed and tested for the power supply of the neutron source device towards BNCT. Experimental results show that this voltage doubling rectifier circuit can satisfy the design requirements, laying a certain foundation for the engineering design of DC high voltage power supply of neutron source device.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2008년도 춘계학술대회논문집
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• pp.695-698
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• 2008

Self-blast circuit breakers utilize the energy dissipated by the arc itself to create the required conditions for arc quenching during the current zero. During the arcing period, high pressure, temperature and radiation of the arc could burn in pure SF6 gas and PTFE nozzle. Ablated nozzle shape and $SF_6$-PTFE mixture vapor affect the performance of an self-blast circuit breaker. After a number of tests, nozzle in circuit breaker is disassembled, a section of ablated nozzle is investigated precisely. Using computational fluid dynamics, the conservation equation for the gas and temperature, velocity and electric fields within breaker is solved. Before applying a section model, developed program is verified with experimental data. Performance of ablated nozzle shape is compared with original model through analysis program.

• Journal of Power Electronics
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• 제6권3호
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• pp.253-263
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• 2006

A high performance and low cost single switch current fed energy recovery circuit (ERC) for an alternating current (AC) plasma display panel (PDP) is proposed. Since it is composed of only one power switch compared with the conventional circuit consisting of four power switches and two large energy recovery capacitors, the ERC features a simpler structure and lower cost. Furthermore, since all power switches can be switched under soft switching operating conditions, the proposed circuit has desirable merits such as increased reliability and low switching loss. Specifically, there are no serious voltage notches across the PDP with the aid of gas discharge current compensation, which can greatly reduce the current stress of all inverter switches, and provide those switches with the turn on timing margin. To confirm the validity of proposed circuit, its operation and performance were verified on a prototype for 7-inch test PDP.