• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.903-906
• /
• 2003

In this paper, we proposed high slew-rate and low-power OP-AMP of the data driver for TFT-LCDs. Proposed OP-AMP contains newly developed rail-to-rail class-AB input circuit which enables the low-quiescent current and high slew-rate OP-AMP. The slew-rate and the quiescent current of the proposed OP-AMP are 31.2V/$\mu$sec and 5$\mu$A, respectively.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1011-1014
• /
• 2003

We proposed a new two-stage operational amplifier that increases the slew rate by adding some simple circuitry to the conventional structure. The proposed circuit is simulated by HSPICE and the slew rate of the proposed circuit is improved more than 10 times than that of conventional one in slewing state without considerable increments in area and power consumption.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.5
• /
• pp.688-696
• /
• 2014

A slew-rate control method of LCD driver ICs is introduced to increase uniformity between adjacent driver ICs and reduce power consumption. The slew rate of every voltage follower is calibrated by a feedback algorithm during the non-displaying period. Under normal operation mode, the slew rate is dynamically controlled for improving power efficiency. Experimental results show that the power consumption is reduced by 16% with a white pattern and by 10% with a black pattern, and display defects are successfully eliminated.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.4
• /
• pp.263-271
• /
• 2013

A low dropout regulator (LDO) with fast transient responses is presented. The proposed LDO eliminates the trade-off between slew rate and unity gain bandwidth, which are the key parameters for fast transient responses. In the proposed buffer, by changing the slew current path, the slew rate and unity gain bandwidth can be controlled independently. Implemented in $0.18-{\mu}m$ high voltage CMOS, the proposed LDO shows up to 200 mA load current with 0.2 V dropout voltage for $1{\mu}F$ output capacitance. The measured maximum transient output voltage variation, minimum quiescent current at no load condition, and maximum unity gain frequency are 24 mV, $7.5{\mu}A$, and higher than 1 MHz, respectively.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2003.07a
• /
• pp.72-75
• /
• 2003

For the analog output buffer in the data driver for large size and high resolution TFT-LCDs, we proposed operational amplifier (op-amp) which contains newly developed transconductance-boosted input stage which enables the low-power consumption and the high slew-rate. The slew-rate and the quiescent current of the proposed op-amp are $6.1V/{\mu}sec$ and $8{\mu}A$, respectively.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2002.08a
• /
• pp.530-532
• /
• 2002

We have developed a low-power, high slew-rate OP-AMP for large size and high resolution TFT-LCDs which have 8${\mu}$A quiescent current with settling time less than 6${\mu}$sec. The proposed OP-AMP contains newly developed the driving circuit of class-AB output stage which can achieve a low quiescent current less than 8${\mu}$A and a slew-rate higher than 3.14V/${\mu}$sec.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2006.10a
• /
• pp.293-316
• /
• 2006

[ $\blacksquare$ ] I/O Signal $\square$ We see adequate margin for the RC B design $\square$ Minimum ODW value is 328ps using Ac to DC measurement for the read case. $\square$ Minimum ODW value is 350ps using AC to DC mesurement method for the write case. $\blacksquare$ CLK Signal $\square$ The slew-rate decreases when the Cterm value increases $\square$ Lower slew-rate could effect delay and jitter. $\square$ There are some ldge issues during transitions with lower Cterm and without Cterm. $\square$ Our recommendation for the Cterm value range is between 1.5pF to 2.4pF. $\blacksquare$ ADD/CMD/Ctrl Signal $\square$ High output slew-rate at low VDD causes ring back that reduces voltage margin because of x-talk. $\square$ 30ohm Rterm for the CTRL signal shows a better signal integrity result compared to 36ohm.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.23 no.4
• /
• pp.431-437
• /
• 2019

PLC(Power Line Communication) is being used in various ways in smart grid system because of the advantages of low cost and high data throughput. However, power line channel has many problems due to impulse noise and various studies have been conducted to solve the problem. Recently, ACDL(Adaptive Cannonical Differential Limiter) which is based on an adaptive clipping with analog nonlinear filter, has been proposed and performs better than the others. In this paper, we show that ACDL is similar to the detection of slew rate with oversampled digital signal by simplification and analysis. Through the simulation under the PRIME standard it is shown that the proposed performs equal to or better than that of ACDL, but significantly reduce the complexity to implement. The BER performance is equal but the complexity is reduced to less than 10%.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2013.10a
• /
• pp.726-729
• /
• 2013

In this paper, low power and high slew rate CMOS rail to rail input/output opamp applicable for ouput buffer amp, in LCD source driver IC, is proposed. Proposed op-amp, is realized the characteristics of low power consumption and high slew rate adding the newly designed control stage of class-B to the conventional output stage of class-AB. From the simulation results, we know that the proposed opamp buffer can drive a 1000pF capacitive load with a 6.5V/us slew-rate, while drawing only the the power consumption of 1.19mW from 3.3V power supply.

• Journal of Power Electronics
• /
• v.4 no.2
• /
• pp.87-95
• /
• 2004

A new fast-response high-current clamp DC-DC converter circuit design is presented that will meet the requirements and features of the new generation of microprocessors and digital systems. The clamp in the proposed converter amplifies the current in case of severe load changes and is able to produce high slew rate of output current and capability to keep constant the output voltage. This proposed high-current clamp technique is theoretically loss less, low cost and easy to implement with simple control scheme. This is modified from a basic buck topology by replacing the output inductor with two magnetically coupled inductors. Inductors are difference in inductance, one has large inductance and other has small inductance. The inductor with small inductance will take over the output inductor during fast load transient. It speedup the output current slew rate and reduce the output voltage drop in the case of heavy burden load changes.