• Proceedings of the KWS Conference
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• 2002.05a
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• pp.65-67
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• 2002

The gas metal arc welding(GMAW) is regarded as one of the best candidate for welding automation in industrial joining application. It is important to monitor the weld quality for the high performance of weld automation. The measured analog signal is frequency analyzed by digital signal process method. In order to observe the welding phenomena and control welding condition, arc light, voltage, and current are measured at the same time. They are analyzed and compared with arc sound. for these experiments, a power source of constant voltage characteristics was used in the pure metal transfer mode.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.4
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• pp.141-147
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• 2014

The wavelet shrinkage is a technique that reduces the wavelet coefficients to minimize the MSE(Mean Square Error) between the signal and the noisy signal by making use of the threshold determined by the variance of the wavelet coefficients. In this paper, by using the monotonic transform and the power of wavelet subbands, new thresholds applicable to the high and the low frequency wavelet bands are proposed, and the thresholds are applied to the ST(soft-threshold) technique to denoise on image signals with additive Gaussian noise. And the results of PSNRs are compared with the results obtained by the VisuShrink technique and those of [15]. The results shows the validity of this technique.

• Journal of Communications and Networks
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• v.6 no.2
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• pp.93-105
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• 2004

This paper discusses cyclostationary interference suppression for multiuser wired communication systems. Crosstalk interference from digital signals in multipair cables has been shown to be cyclostationary. Many crosstalk equalization or suppression techniques have been proposed which make implicit use of the cyclostationarity of the crosstalk interferer. In this paper, the convergence and steady-state behaviors of a fractionally spaced equalizer (FSE) in the presence of multiple cyclostationary crosstalk interference are thoroughly analyzed by using the equalizer's eigenstructure. The eigenvalues with multiple cyclostationary interference depend upon the folded signal and interferer power spectra, the cross power spectrum between the signal and the interferer, and tile cross power spectrum between the interferers, which results in significantly different initial convergence and steady-state behaviors as compared to the stationary noise case. The performance of the equalizer varies depending on the relative clock phase of the symbol clocks used by the signal and multiple interferers. Measued characteristics as well as analytical model of NEXT/FEXT channel are used to compute the optimum and worst relative clock phases among the signal and multiple interferers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.227-232
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• 2009

The simple PSK signal generation method using a quadrature hybrid coupler and reflection coefficient elements was analyzed in this paper. The PSK modulation signal with a constant constellation is generated by reflection coefficient from 90o hybrid coupler output ports, the high-mode PSK signal is also generated by the hybrid structure of coupler, delay line and power combiner. The BPSK signal is simply generated by a 90o hybrid coupler and reflection elements, and QPSK with 90o phase constellation is generated by additional delay line and power combiner. By simulation results, the generated PSK signals by the proposed circuit get good modulation spectra within 3o phase error.

• Journal of the Semiconductor & Display Technology
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• v.18 no.1
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• pp.59-64
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• 2019

Recently, time synchronous has become important for satellite launch control facilities, multiple thermal power plants, and power system facilities. Information from time synchronous at each of these industrial sites requires time synchronization to control or monitor the system with correlation. In this paper, IRIG-B codes, which can be used for time synchronous, are used as specifications in IRIG standard 200-16. Signals from IRIG-B120 (Analog), IRIG-B000 (Digital), and one PPS are output from GPS receiver. Using the signal from IRIG-B120 (Analog), it passes through the signal from the analog amplifier and generates one PPS signal using the field-programmable gate array. The FPGA is used cyclone EPM570T100I5N. According to IEEE regulations, the error of one PPS is specified within 1us, but in this paper, the error is within 100ns. The output of the one PPS signal was then compared and tested against the one PPS signal on the GPS receiver to verify accuracy and reliability. In addition, the proposed time synchronous is simple to construct and structure, easy to implement, and provides high time precision compared to typical time synchronous. The output of the one PPS signals and IRIG-B000 signal will be used in many industry sectors.

• ETRI Journal
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• v.30 no.3
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• pp.451-460
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• 2008

Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low-power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low-power commutators based on an advanced interconnection, and parallel-pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel-pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.1
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• pp.27-33
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• 2001

This paper presents a digital instrument for a DSP based power quality analysis in three phase power system where current waveform is non-sinusoidal. it is based on stand alone type TMS320C31 DSP(digital signal processor)board and on a special high-speed data acquisition system. Power quality of low power motor drives are analyzed and processed by using a simple average power algorithm, and result of power analysis are displayed by LCD in the proposed system. This paper also goes on to discuss the performance of an instrument prototype, both in terms of accuracy and speed of measurement under the transient and steady state condition.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.239-242
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• 1999

In this paper, we report the process/device design of high-speed, high-voltage SOI smart power IC for mobile communication system, high-speed HDD system and the electronic control system of automobiles. The high voltage LDMOS with 70V breakdown voltage under 0.8${\mu}{\textrm}{m}$ design rule, the high voltage bipolar with 40V breakdown voltage for analog signal processing, the high speed bipolar with cut-off frequency over 20㎓ and LDD NMOS for high density were proposed and simulated on a single chip by the simulator DIOS and DESSIS. And we extracted the process/device parameters of the simulated devices.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.1
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• pp.33-41
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• 2019

We propose an embedded solution to design a high-speed and high-accuracy 16bit analog-digital signal processing interface for the control systems using various external analog signals. Choosing TMS320F28377D micro controller unit (MCU) featuring high-performance processing in the 32-bit floating point operation, low power consumption, and various I/O device supports, we design and build the proposed system that supports both 16-bit analog-digital converter (ADC) interface and high precision digital-analog converter (DAC) interface. The ADC receives voltage-level differential signals from fully differential amplifiers, and the DAC communicates with MCU through 50 MHz bandwidth high-fast serial peripheral interface (SPI). We port the boot loader and device drivers to the implemented board, and construct the firmware development environment for the application programming. The performance of the entire implemented system is demonstrated by analog-digital signal processing tests, and is verified by comparing the test results with those of existing similar systems.

• Journal of Power Electronics
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• v.8 no.4
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• pp.332-344
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• 2008

High frequency AC (HFAC) power distribution systems delivering power through a high frequency AC link with sinusoidal voltage have the advantages of simple structure and high efficiency. In a multiple module system, where multiple resonant inverters are paralleled to the high frequency AC bus through connection inductors, it is necessary for the output voltage phase angles of the inverters be controlled so that the circulating current among the inverters be minimized. However, the phase angle of the resonant inverters output voltage can not be controlled with conventional phase shift modulation or pulse width modulation. The phase angle is a function of both the phase of the gating signals and the impedance of the resonant tank. In this paper, we proposed a pulse phase modulation (PPM) concept for the resonant inverters, so that the phase angle of the output voltage can be regulated. The PPM can be used to minimize the circulating current between the resonant inverters. The mechanisms of the phase angle control and the PPM were explained. The small signal model of a PPM controlled half-bridge resonant inverter was analyzed. The concept was verified in a half bridge resonant inverter with a series-parallel resonant tank. An HFAC power distribution system with two resonant inverters connected in parallel to a 500kHz, 28V AC bus was presented to demonstrate the applicability of the concept in a high frequency power distribution system.