• 제목/요약/키워드: High level synthesis

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중학교 수학 교과서 문제의 인지적 영역 분석 (Cognitive Domain of Problems in Korea Mathematics Textbooks)

  • 이지혜;허유진;신민경;허난
    • East Asian mathematical journal
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    • 제35권4호
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    • pp.451-465
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    • 2019
  • Textbooks are official materials so that these are the most frequently used teaching materials in school. The teacher constructs the lesson based on the contents of the textbook to achieve the learning goal. Thus, textbooks play an important role because the quality of the contents in textbooks affects the cognitive level of students. This study investigates the cognitive domain based on Bloom's Taxonomy of Educational Objectives(knowledge, understanding, application, analysis, synthesis and evaluation) of 'Values and Expression' in the mathematics textbook of the first grade of middle school reflecting the 2015 revised mathematics curriculum. We also looked at cognitive levels based on Bloom's Taxonomy of Educational Objectives. As a result, it was found that understanding was dominant in 'Values and Expression'. Also, although the problem of requiring a higher level of cognition is increasing as the unit finishes, there are still a high percentage of low level of problems.

우주용 냉각기의 미소진동을 이용한 에너지 수확 시스템의 실험적 성능검증 (Experimental Performance Verification of Energy-Harvesting System Using the Micro-vibration of the Spaceborne Cryocooler)

  • 정현모;권성철;오현웅
    • 항공우주시스템공학회지
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    • 제10권3호
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    • pp.15-22
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    • 2016
  • The on-board appendages of satellites with mechanical moving parts such as the fly-wheel, the control-moment gyro, the cryocooler, and the gimbal-type directional antenna can generate an undesirable micro-vibration disturbance, which is one of the main causes of the image-quality degradation that affects high-resolution observation satellites. Consequently, the isolation of the micro-vibration issue has always been considered as salient, and the micro-vibration is therefore the focus of this study wherein a complex system that can provide the dual functions of a guaranteed vibration-isolation performance and electrical energy harvesting is proposed. The vibration-isolation and energy-harvesting performances of the complex system are predicted through a numerical analysis based on the characteristics that are obtained from component-level tests. In addition, the effectiveness of the complex system that is proposed in this study is verified through an assembly-level functional-performance test.

Multi-Objective Pareto Optimization of Parallel Synthesis of Embedded Computer Systems

  • Drabowski, Mieczyslaw
    • International Journal of Computer Science & Network Security
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    • 제21권3호
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    • pp.304-310
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    • 2021
  • The paper presents problems of optimization of the synthesis of embedded systems, in particular Pareto optimization. The model of such a system for its design for high-level of abstract is based on the classic approach known from the theory of task scheduling, but it is significantly extended, among others, by the characteristics of tasks and resources as well as additional criteria of optimal system in scope structure and operation. The metaheuristic algorithm operating according to this model introduces a new approach to system synthesis, in which parallelism of task scheduling and resources partition is applied. An algorithm based on a genetic approach with simulated annealing and Boltzmann tournaments, avoids local minima and generates optimized solutions. Such a synthesis is based on the implementation of task scheduling, resources identification and partition, allocation of tasks and resources and ultimately on the optimization of the designed system in accordance with the optimization criteria regarding cost of implementation, execution speed of processes and energy consumption by the system during operation. This paper presents examples and results for multi-criteria optimization, based on calculations for specifying non-dominated solutions and indicating a subset of Pareto solutions in the space of all solutions.

데이타 상관 증가에 의한 저전력 상위 수준 합성 (Low power high level synthesis by increasing data correlation)

  • 신동완;최기영
    • 전자공학회논문지C
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    • 제34C권5호
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    • pp.1-17
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    • 1997
  • With the increasing performance and density of VLSI scircuits as well as the popularity of portable devices such as personal digital assitance, power consumption has emerged as an important issue in the design of electronic systems. Low power design techniqeus have been pursued at all design levels. However, it is more effective to attempt to reduce power dissipation at higher levels of abstraction which allow wider view. In this paper, we propose a simultaneous scheduling and binding scheme which increases the correlation between cosecutive inputs to an operation so that the switched capacitance of execution units is reduced in datapath-dominated circuits. The proposed method is implemented and integrated into the scheduling and assignment part of HYPER synthesis environment. Compared with original HYPER synthesis system, average power saving of 23.0% in execution units and 14.2% in the whole circuits, ar eobtained for a set of benchmark examples.

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압축센싱 디지털 수신기 신호처리 로직 구현 (Signal Processing Logic Implementation for Compressive Sensing Digital Receiver)

  • 안우현;송장훈;강종진;정웅
    • 한국군사과학기술학회지
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    • 제21권4호
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    • pp.437-446
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    • 2018
  • This paper describes the real-time logic implementation of orthogonal matching pursuit(OMP) algorithm for compressive sensing digital receiver. OMP contains various complex-valued linear algebra operations, such as matrix multiplication and matrix inversion, in an iterative manner. Xilinx Vivado high-level synthesis(HLS) is introduced to design the digital logic more efficiently. The real-time signal processing is realized by applying dataflow architecture allowing functions and loops to execute concurrently. Compared with the prior works, the proposed design requires 2.5 times more DSP resources, but 10 times less signal reconstruction time of $1.024{\mu}s$ with a vector of length 48 with 2 non-zero elements.

스위칭 동작 최소화를 통한 저전력 데이터 경로 최적화 (A Low Power-Driven Data Path Optimization based on Minimizing Switching Activity)

  • 임세진;조준동
    • 전자공학회논문지C
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    • 제36C권4호
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    • pp.17-29
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    • 1999
  • 본 논문은 데이터 의존적인 CMOS 회로(예: DSP) 의 전력량을 감축하기 위한 상위 수준 합성 기법에 대한 연구이다. 상위수준 합성은 스케줄링, 자원 및 레지스터 할당의 세가지로 나우어서 수행한다. 스케줄링시의 저전력 설계의 목적은 자원할당 시 입력을 재 사용할 수 있는 가능성을 증가시키는 것이다. 스케줄링 후에 자원 및 레지스터 할당 문제는 가중차기 부가된 앙립 그래프로 표현하여 최소비용흐름 알고리즘을 수행함으로써 스위칭 동작횟수가 적은 해를 얻는다. 제안된 알고리즘은 저전력 레지스터 및 자원 할당 문제에 대하여 O({{{{ { n}^{3 } }}}}) (n은 그래프의 노드수) 시간에 최적해를 제공한다. 벤치마크 회로에 대한 실험 결과는 15%의 전력 감축 효과를 나타낸다.

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저 전력 아키텍처를 위한 상위 레벨 데이터 패스 할당 알고리즘 (A High-Level Data Path Allocation Algorithm for Low Power Architecture)

  • 인치호
    • 전기전자학회논문지
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    • 제7권2호
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    • pp.166-171
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    • 2003
  • 본 논문은 상위 레벨 합성에서의 레지스터와 자원 할당 과정의 스위치 동작 최소화를 통한 저 전력 데이터 패스 할당 알고리즘을 제안한다. 제안하는 알고리즘은 스케줄링된 CDFG를 입력으로 할당 과정에서 전력 최소화를 수행한다. 알고리즘은 레지스터 할당과 자원 할당 과정을 나누어 수행한다. 레지스터 할당 알고리즘은 기능 장치내의 불필요한 스위칭 동작을 제거하고 멀티플렉서의 수를 최소화한다. 자원 할당 과정은 스위칭 동작을 최소화할 수 있는 연산자의 순서를 선택한다. 본 논문에서 제안하는 알고리즘과 genesis-lp 상위 레벨 합성시스템을 벤치마크를 이용한 비교 실험결과 평균 15.3%의 전력 감소효과가 있다.

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HLS 를 활용한 FPGA 기반의 FALCON 알고리즘 서명 생성 하드웨어 가속 연구 (FPGA-based Hardware Acceleration for Signature Generation of FALCON using High Level Synthesis)

  • 이용석;이윤지;백윤흥
    • 한국정보처리학회:학술대회논문집
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    • 한국정보처리학회 2024년도 춘계학술발표대회
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    • pp.374-376
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    • 2024
  • 최근 차세대 암호로 불리는 양자내성암호(PQC, Post Quantum Cryptography)는 양자 컴퓨터와 현재 사용하는 일반 컴퓨터 모두에서 내성을 갖는 암호이다. 그 중 FALCON 전자 서명 알고리즘은 표준화로 선정되며 초안 문서를 작성하는 중으로 차세대 암호로 주목받고 있다. 하지만 FALCON 알고리즘은 실수 연산을 사용하는 등 임베디드 환경에서 효율적인 성능을 보이지 못하고 있다. 이에 따라 임베디드 하드웨어 가속 연구들이 있으며, 그 중 HLS(High Level Synthesis)를 통한 FPGA 가속 연구들이 있다. 본 논문에서는 FALCON 전자서명 알고리즘에서 HLS 로 구현하는데 어려움이 있었던 서명 생성 함수에 대해 분석하고, 이를 소프트웨어/하드웨어 통합설계를 통해 HLS로 구현하였다. 이는 기존 소프트웨어 대비 약 10배 빠른 연산 속도를 보여주고 있다.

Synthesis and High Expression of Chitin Deacetylase from Colletotrichum lindemuthianum in Pichia pastoris GS115

  • Kang, Lixin;Chen, Xiaomei;Zhai, Chao;Ma, Lixin
    • Journal of Microbiology and Biotechnology
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    • 제22권9호
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    • pp.1202-1207
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    • 2012
  • A gene, ClCDA, encoding chitin deacetylase from Colletotrichum lindemuthianum, was optimized according to the codon usage bias of Pichia pastoris and synthesized in vitro by overlap extension PCR. It was secretorily expressed in P. pastoris GS115 using the constitutive expression vector pHMB905A. The expression level reached the highest with 110 mg/l culture supernatant after 72 h of methanol induction, which comprised 77.27 U/mg chitin deacetylase activity. SDS-PAGE, mass spectrometry, and deglycosylation assays demonstrated that partial recombinant protein was glycosylated with an apparent molecular mass of 33 kDa. The amino acid sequences of recombinant proteins were confirmed by mass spectrometry.

Continuous Synthesis of Escherichia coli GroEL at a high Temperature

  • Kwak, Young-Hak;Lee, Kyong-Sun;Kim, Ji-Yeon;Lee, Dong-Seok;Kim, Han-Bok
    • Journal of Microbiology
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    • 제38권3호
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    • pp.145-149
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    • 2000
  • GroEL is a typical molecular chaperone. GroEL synthesis patterns at various culture temperatures in Escherichia coli were investigated in this study. No significant differences in the amount of GroEL produced from the chromosome were found at 30 and 37$^{\circ}C$. However, GroEL production increased 3.4-fold at 42$^{\circ}C$. GroEL synthesis was not transient but continuous at 42$^{\circ}C$, although most heat shock gene expression is known to be transient. To understand the role of the groEL structural gene, a groE promoter-lacZ fusion was constructed. Interestingly , while transcriptional fusion is not thermally inducible, it is inducible by ethanol, suggesting that the secondary structure of the groEL transcript is involved in thermal regulation of the groEL gene. Secondary structures of groE mRNA at 37 and 42$^{\circ}C$ were compared using the computer program RNAdraw. Distinct structures at the two temperatures were found, and these structures may be related to a high level of GroEL expression at 42$^{\circ}C$.

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