• Transactions on Electrical and Electronic Materials
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• 제15권6호
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• pp.328-332
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• 2014

Thin film transistors (TFTs) with an amorphous silicon zinc tin oxide (a-2SZTO) channel layer have been fabricated using an RF magnetron sputtering system. The effect of the change of excitation electron on the variation of the total interfacial trap states of a-2SZTO systems was investigated depending on sputtering power, since the interfacial state could be changed by changing sputtering power. It is well known that Si can effectively reduce the generation of the oxygen vacancies. However, The a-2SZTO systems of ZTO doped with 2 wt% Si could be degraded because the Si peripheral electron belonging to a p-orbital affects the amorphous zinc tin oxide (a-ZTO) TFTs of the s-orbital overlap structure. We fabricated amorphous 2 wt% Si-doped ZnSnO (a-2SZTO) TFTs using an RF magnetron sputtering system. The a-2SZTO TFTs show an improvement of the electrical property with increasing power. The a-2SZTO TFTs fabricated at a power of 30 W showed many of the total interfacial trap states. The a-2SZTO TFTs at a power of 30 W showed poor electrical property. However, at 50 W power, the total interfacial trap states showed improvement. In addition, the improved total interfacial states affected the thermal stress of a-2SZTO TFTs. Therefore, a-2SZTO TFTs fabricated at 50 W power showed a relatively small shift of threshold voltage. Similarly, the activation energy of a-2SZTO TFTs fabricated at 50 W power exhibits a relatively large falling rate (0.0475 eV/V) with a relatively high activation energy, which means that the a-2SZTO TFTs fabricated at 50 W power has a relatively lower trap density than other power cases. As a result, the electrical characteristics of a-2SZTO TFTs fabricated at a sputtering power of 50 W are enhanced. The TFTs fabricated by rf sputter should be carefully optimized to provide better stability for a-2SZTO in terms of the sputtering power, which is closely related to the interfacial trap states.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.407-418
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• 2014

As the high-throughput requirement in the next generation communication system increases, it becomes essential to implement high-throughput SISO (Soft-Input Soft-Output) decoder with minimal hardware resources. In this paper, we present the comparison results between cascaded radix-4 ACS (Add-Compare-Select) and LUT (Look-Up Table)-based radix-4 ACS in terms of delay, area, and power consumption. The hardware overhead incurred from the retiming technique used for high speed radix-4 ACS operation is also analyzed. According to the various analysis results, high-throughput radix-4 SISO decoding architecture based on simple path metric recovery circuit is proposed to minimize the hardware resources. The proposed architecture is implemented in 65 nm CMOS process and memory requirement and power consumption can be reduced up to 78% and 32%, respectively, while achieving high-throughput requirement.

• 대한전자공학회논문지SD
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• 제37권11호
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• pp.59-66
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• 2000

본 논문에서는 DSP에서 필수적인 고속 저 전력 조건 선택 덧셈기/뺄셈기의 마크로 셀 라이브러리를 설계, 구축하였다. 덧셈기의 Carry전달 지연 시간을 최소로 하기 위한 CLA 기법과 연산 가능한 모든 결과 값을 미리 계산한 후 선택하는 조건 선택 기법을 적용하였다. 또한 이러한 설계방법이 8비트에서 64비트까지 자동 생성될 수 있도록 전용 프로그램을 작성하고 셀 기반 설계기법을 도입하여 Auto P&R Tool과 연계하여 자동으로 레이아웃이 가능하도록 하였다. 제안된 덧셈기/뺄셈기는 0.25${\mu}m$, 1-Poly, 5-Metal, N-well CMOS 공정을 사용하여 제작되었으며, 2.5V 단일 공급전압에서 지연시간, 소모 전력을 측정하였다. 측정결과 32 비트 덧셈기/뺄셈기의 경우 3.43ns의 지연시간과 42.8${\mu}w$/MHz의 전력소비를 나타내었다.

• 전력전자학회논문지
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• 제14권5호
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• pp.423-430
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• 2009

최근 저압 배전계통에서 사용되고 있는 과부하겸용 누전차단기 즉, RCD의 저조한 응답특성으로 인한 전기화재 원인의 대부분을 차지하는 단락사고 및 과부하사고에 대한 대응이 매우 미흡한 실정이다. 이에 본 논문에서는 기존 RCD에 대한 모의 사고실험을 통하여 그 비신뢰성을 확인하고, 이러한 RCD의 단점을 개선하고자 내구성과 속응성이 우수한 반도체 스위칭 소자들과 고정밀 전류센서를 이용한 "전기화재 방재장치(EFDPD : Electrical Fire Disaster Prevention Device)"를 제안하여 저압 배전계통에서의 단락 및 과부하사고로 인한 전기재해를 방지하고자 한다. 제안한 장치의 고정밀 전류센서로 사용된 리드스위치는 각종 전기사고에서 수반되는 단락전류 및 과전류에 의한 배전선로의 상승된 자속을 정밀 감지한 후, 자체 차단장치를 동작시키는 원리를 가진다. 다양한 동작특성 분석을 통하여 기존의 차단기와 비교하여 차단동작 응답속도와 그 신뢰성이 입증된다. 이로써 제안한 전기안전 제어장치는 기존 RCD들의 빈번한 오동작과 비신뢰성, 저조한 응답특성으로 인한 각종 전기사고 및 전기화재의 발생을 방지하고자 한다.

• 마이크로전자및패키징학회지
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• 제30권1호
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• pp.63-70
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• 2023

오늘날 심각한 환경 오염과 에너지의 중요성으로 전력 반도체의 중요도가 지속적으로 높아지고 있다. 특히 wide band gap(WBG)소자 중 하나인 SiC-MOSFET은 우수한 고전압 특성을 가지고 있어 그 중요도가 매우 높다. 하지만 SiC-MOSFET의 전기적 특성이 열에 민감하기 때문에 패키지를 통한 열 관리가 필요하다. 본 논문에서는 기존 전력 반도체에서 사용하는 direct bonded copper(DBC) 기판 방식이 아닌 insulated metal substrate(IMS) 방식을 제안한다. IMS는 DBC에 비해 공정이 쉬우며 coefficient of thermal expansion (CTE)가 높아서 비용과 신뢰성 측면에서 우수하다. IMS의 절연층인 dielectric film의 열전도도가 낮은 문제가 있지만 매우 얇은 두께로 공정이 가능하기 때문에 낮은 열 전도도를 충분히 극복할 수 있다. 이를 확인하기 위해서 이번 연구에서는 electric-thermal co-simulation을 수행하였으며 검증을 위해 DBC 기판과 IMS를 제작하여 실험하였다.

• Journal of Electrical Engineering and Technology
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• 제12권4호
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• pp.1484-1494
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• 2017

We present a two-stage inverter with high step-up conversion ratio engaging modified finite-set Model Predictive Control (MPC) for utility-integrated photovoltaic (PV) applications. The anticipated arrangement is fit for low power PV uses, the calculated efficiency at 150 W input power and 19 times boosting ratio was around 94%. The suggested high-gain dc-dc converter based on Cockcroft-Walton multiplier constitutes the first-stage of the offered structure, due to its high step-up ability. It can boost the input voltage up to 20 times. The 3S current-source inverter constitutes the second-stage. The 3S current-source inverter hires three semiconductor switches, in which one is functioning at high-frequency and the others are operating at fundamental-frequency. The high-switching pulses are varied in the procedure of unidirectional sine-wave to engender a current coordinated with the utility-voltage. The unidirectional current is shaped into alternating current by the synchronized push-pull configuration. The MPC process are intended to control the scheme and achieve the subsequent tasks, take out the Maximum Power (MP) from the PV, step-up the PV voltage, and introduces low current with low Total Harmonic Distortion (THD) and with unity power factor with the grid voltage.

• Journal of Power Electronics
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• 제16권4호
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• pp.1245-1255
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• 2016

The single resonant inverter is widely employed in typical inductive power transfer (IPT) systems to generate a high-frequency current in the primary side. However, the power capacity of a single resonant inverter is limited by the constraints of power electronic devices and the relevant cost. Consequently, IPT systems fail to meet high-power application requirements, such as those in rail applications. Total harmonic distortion (THD) may also violate the standard electromagnetic interference requirements with phase shift control under light load conditions. A power regulation approach with selective harmonic elimination is proposed on the basis of a parallel multi-inverter to upgrade the power levels of IPT systems and suppress THD under light load conditions by changing the output voltage pulse width and phase shift angle among parallel multi-inverters. The validity of the proposed control approach is verified by using a 1,412.3 W prototype system, which achieves a maximum transfer efficiency of 90.602%. Output power levels can be dramatically improved with the same semiconductor capacity, and distortion can be effectively suppressed under various load conditions.

• 한국항행학회논문지
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• 제22권4호
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• pp.319-324
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• 2018

본 논문은 RF 전력 반도체를 사용한 고출력 전력증폭기를 구현한 것으로 기존의 플라즈마 발생 장치에 사용되는 마그네트론 방식의 고출력 증폭기 문제점인 낮은 효율과 짧은 수명, 유지 보수의 어려움 그리고 높은 운용비용 등을 개선하기 위한 것이다. 구현된 고출력 전력증폭기는 2.45 GHz ISM (industrial scientific medical) 대역에서 공간 결합방식을 이용한 저 손실, 고출력 레디알 결합기와 반도체로 3 kW급 출력을 얻기 위해서 300 W 급 전력 증폭기 16개의 증폭기로 구성되어 있다. 또한, 이 증폭기는 개별적인 증폭기에 수냉 방식의 구조를 적용하여 고출력에 따른 발열문제를 극복하였다. 소형 시스템으로 구성된 이 전력증폭기는 원하는 출력에서 50%의 높은 효율을 얻었다.

• ETRI Journal
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• 제30권6호
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• pp.783-789
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• 2008

A bio-inspired vision chip for edge detection was fabricated using 0.35 ${\mu}m$ double-poly four-metal complementary metal-oxide-semiconductor technology. It mimics the edge detection mechanism of a biological retina. This type of vision chip offer several advantages including compact size, high speed, and dense system integration. Low resolution and relatively high power consumption are common limitations of these chips because of their complex circuit structure. We have tried to overcome these problems by rearranging and simplifying their circuits. A vision chip of $160{\times}120$ pixels has been fabricated in $5{\times}5\;mm^2$ silicon die. It shows less than 10 mW of power consumption.

• 전기학회논문지
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• 제56권7호
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• pp.1282-1287
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• 2007

We investigated the damage of the CMOS IC which manufactured three different technologies by high power microwave. The tests separated the two methods in accordance with the types of the CMOS IC located inner waveguide. The only CMOS IC which was located inner waveguide was occurred breakdown below the max electric field (23.94kV/m) without destruction but the CMOS IC which was connected IC to line organically was located inner waveguide and it was occurred breakdown and destruction below the max electric field. Also destructed CMOS IC was removed their surface and a chip condition was analyzed by SEM. The SEM analysis of the damaged devices showed onchuipwire and bondwire destruction like melting due to thermal effect. The tested results are applied to the fundamental data which interprets the combination mechanism of the semiconductors from artificial electromagnetic wave environment and are applied to the data which understand electromagnetic wave effects of electronic equipments.