• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.286-288
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• 2007

The proposed method offers an improved control method for high power density AC/DC adapter by using more energy efficient electrical equipments. Power factor corrector (PFC) topology is based on boost topology with boundary conduction mode (BCM). DC/DC topology is based on half-bridge topology with newly introduced off-time control method, which helps to reduce size of the semiconductor and the magnetic devices. Test results with 85W AC/DC adapter (18.5V/4.6A) design shows that the measured efficiency is 90% with power density of $36W/in^3$. It also show low no load power consumption of about 0.5W.

• Journal of Power Electronics
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• 제16권1호
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• pp.111-120
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• 2016

Generally, a single phase H-bridge converter feeding a single primary track is employed in conventional inductive power transfer systems. However, these systems may not be suitable for some high power applications due to the constraints of the semiconductor switches and the cost. To resolve this problem, a novel dual coupled primary tracks IPT system consisting of two high frequency resonant inverters feeding the tracks is presented in this paper. The primary tracks are wound around an E-shape ferrite core in parallel which enhances the magnetic flux around the tracks. The mutual inductance of the coupled tracks is utilized to achieve adjustable power sharing between the inverters by configuring the additional resonant capacitors. The total transfer power can be continuously regulated by altering the pulse width of the inverters' output voltage with the phase shift control approach. In addition, the system's efficiency and the control strategy are provided to analyze the characteristic of the proposed IPT system. An experimental setup with total power of 1.4kW is employed to verify the proposed system under power ratios of 1:1 and 1:2 with a transfer efficiency up to 88.7%. The results verify the performance of the proposed system.

• Transactions on Electrical and Electronic Materials
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• 제14권1호
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• pp.47-51
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• 2013

A high power MOSFET switch based on a 0.35 ${\mu}m$ CMOS process has been developed for the protection IC of a rechargeable battery. In this process, a vertical double diffused MOS (VDMOS) using 3 ${\mu}m$-thick epi-taxy layer is integrated with a Zener diode. The p-n+Zener diode is fabricated on top of the VDMOS and used to protect the VDMOS from high voltage switching and electrostatic discharge voltage. A fully integrated digital circuit with power devices has also been developed for a rechargeable battery. The experiment indicates that both breakdown voltage and leakage current depend on the doping concentration of the Zener diode. The dependency of the breakdown voltage on doping concentration is in a trade-off relationship with that of the leakage current. The breakdown voltage is obtained to exceed 14 V and the leakage current is controlled under 0.5 ${\mu}A$. The proposed integrated module with the application of the power MOSFET indicates the high performance of the protection IC, where the overcharge delay time and detection voltage are controlled within 1.1 s and 4.2 V, respectively.

• 반도체디스플레이기술학회지
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• 제11권2호
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• pp.7-11
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• 2012

SiNx films have been wildly used as anti-reflection coatings and passivation for crystalline silicon solar cells. In this study, the SiNx films were deposited by using high frequency (13.56MHz) PECVD and optical & passivation properties were investigated. The RF power was changed in a certain range for the film deposition. Then, the refractive index, etch rate, minority carrier lifetime and cell efficiency were measured to study the properties of the film respectively. The optimal deposition conditions for application to crystalline silicon solar cells were proposed as results of the study. Finally, the best cell efficiency of 16.98% was obtained from the solar cell with the SiNx films deposited by RF power of 550W.

• 반도체디스플레이기술학회지
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• 제22권3호
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• pp.155-160
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• 2023

The potential performance benefits of Silicon Carbide(SiC) MOSFETs in high power, high frequency power switching applications have been well established over the past 20 years. In the past few years, SiC MOSFET offerings have been announced by suppliers as die, discrete, module and system level products. In high-voltage SiC vertical devices, major design concerns is the edge termination and cell pitch design Field Limiting Rings(FLR) based structures are commonly used in the edge termination approaches. This study presents a comprehensive analysis of the impact of variation of FLR and JFET region on the performance of a 3.3 kV SiC MOSFET during. The improvement in MOSFET reverse bias by optimizing the field ring design and its influence on the nominal operating performance is evaluated. And, manufacturability of the optimization of the JFET region of the SiC MOSFET was also examined by investigating full-map electrical characteristics.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.438-445
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• 2017

This paper presents a low-power high-resolution band-pass ${\Sigma}{\Delta}$ ADC for accelerometer applications. The proposed band-pass ${\Sigma}{\Delta}$ ADC consists of a high-performance 6-th order feed-forward ${\Sigma}{\Delta}$ modulator with 1-bit quantization and a low-power, area-efficient digital filter. The ADC is fabricated in 180 nm 1P6M mixed-signal CMOS process with a die area of $5mm^2$. This high-resolution ADC got 90 dB peak signal to noise plus distortion ratio (SNDR) and 96 dB dynamic range (DR) over 4 kHz bandwidth, while the intermediate frequency (IF) is shifting from 100 KHz to 200 KHz. The power dissipation of the chip is 5.6 mW under 1.8 V (digital)/3.3 V (analog) power supply.

• 전력전자학회논문지
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• 제20권4호
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• pp.337-343
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• 2015

The multi-level inverters are highly efficient for high-power and medium-voltage AC driving applications, such as high-speed railway systems and renewable energy resources, because such inverters generate lower total harmonic distortion (THD) and electromagnetic interface (EMI). Lower switching stress occurs on switching devices compared with conventional two-level inverters. Depending on the multi-level inverter topology, the required components and number of switching devices are different, influencing the overall efficiency. Comparative studies of multi-level inverters based on loss analysis and output characteristic are necessary to apply multi-level inverters in high-power AC conversion systems. This paper proposes a theoretical loss analysis method based on piecewise linearization of characteristic curves of power semiconductor devices as well as loss analysis and output performance comparison of five-level neutral-point clamped, flying capacitor inverters, and high-level cascaded H-bridge multi-level inverters.

• ETRI Journal
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• 제36권5호
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• pp.829-834
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• 2014

In this paper, a lateral power metal-oxide-semiconductor field-effect transistor with ultra-low specific on-resistance is proposed to be applied to a high-voltage (up to 200 V) integrated chip. The proposed structure has two characteristics. Firstly, a high level of drift doping concentration can be kept because a tilt-implanted p-drift layer assists in the full depletion of the n-drift region. Secondly, charge imbalance is avoided by an extended trench gate, which suppresses the trench corner effect occurring in the n-drift region and helps achieve a high breakdown voltage (BV). Compared to a conventional trench gate, the simulation result shows a 37.5% decrease in $R_{on.sp}$ and a 16% improvement in BV.

• Korean Chemical Engineering Research
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• 제62권3호
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• pp.225-232
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• 2024

탄소 중립 사회로의 전환을 위해 전체 온실가스 배출량의 86.8%를 차지하는 에너지 생산 부문에서의 이산화탄소 배출량 감축이 필요하다. 현재 우리나라는 총 발전량의 60%를 석탄과 천연가스에 의존하고 있으며 이를 풍력, 태양광 등의 재생에너지로 대체하는 방법은 에너지 수급이 불안정하고 비용이 높다는 단점이 있다. 이를 해결하기 위해 본 연구에서는 기존에 사용되고 있는 NGCC(Natural Gas Combined Cycle) 공정을 기반으로 천연가스, 암모니아, 수소를 혼합하여 연소한다는 해결책을 제시하였다. 시뮬레이션을 수행한 결과, 이산화탄소 배출량을 효과적으로 줄일 수 있었으며 천연가스만을 연료로 이용해 얻은 전력량과 비교하였을 때 34%~238%의 전력을 얻었다. 천연가스, 암모니아, 수소의 질량분율에 대한 사례연구를 수행한 결과, 암모니아 비율이 증가할수록 발전량과 NO_x 배출량은 감소하였고 수소비율이 증가할수록 발전량과 NO_x 배출량은 증가하였다. 본 연구는 추후 다양한 혼합 연료의 조합 및 경제성 평가 등 혼합 연료 발전 분야의 가이드라인이 될 수 있을 것이다.

• 한국진공학회지
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• 제15권6호
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• pp.630-636
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• 2006

플래시 메모리 반도체의 고집적화와 고밀도화가 진행함에 따라 플래시 메모리의 트랜지스터 안 선폭을 중심으로 게이트 패턴의 미세화가 진행 중이다. 최근 100 nm 이하의 선폭을 구현하기 위해서 ONO(oxide-nitride-oxide)를 사용하기 위한 연구가 개발 중이고, 이러한 100 nm이하의 미세 선폭으로 갈수록 식각 속도와 식각의 프로파일은 중요한 요인으로 작용하고 있다. ICP 식각 장비를 이용하여, power를 50 W 증가 하였을 때, 각각 식각 속도와 포토레지스트와의 선택비를 확인 한 결과 platen power를 100 W로 올렸을 경우 가장 좋은 결과를 나타내었다. 100 W에서 HBr가스의 유량에 변화를 주었을 경우 가스의 양을 증가 할수록 식각 속도는 감소하였지만, 포토레지스트와의 선택비는 증가함을 보였다. 유도결합 플라즈마 식각 장비를 가지고 platen power를 100 W, HBr gas를 35 sccm 공급하여 하부 층에 노치가 형성이 안되고, 식각 속도 320 nm/min, 감광액과의 선택비 3.5:1, 측면식각 프로파일이 수직인 공정 조건을 찾았다.