• Korean Journal of Materials Research
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• v.29 no.12
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• pp.753-756
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• 2019

Orthorhombic dysprosium manganite DyMnO₃ with single phase is synthesized using solid-state reaction technique and the crystal structure and dielectric properties as functions of temperature and frequency are investigated. Thermally activated dielectric relaxations are shown in the temperature dependence of the complex permittivity, and the respective peaks are found to be shifted to higher temperatures as the measuring frequency increases. In Arrhenius plots, activation energies of 0.32 and 0.24 eV for the high- and low-temperature relaxations are observed, respectively. Analysis of the relationship between the real and imaginary parts of the permittivity and the frequencies allows us to explain the dielectric behavior of DyMnO₃ ceramics by the universal dielectric response model. A separation of the intrinsic grain and grain boundary properties is achieved using an equivalent circuit model. The dielectric responses of this circuit are discerned by impedance spectroscopy study. The determined grain and grain boundary effects in the orthorhombic DyMnO₃ ceramics are responsible for the observed high- and low-temperature relaxations in the dielectric properties.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.4
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• pp.322-332
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• 2022

Energy storage capacitors based on dielectric ceramics with superior polarization properties and dielectric constant can provide much higher output power density due to their very fast energy charging/discharging rates, which are particularly suitable for operating pulsed-power devices. For an outstanding energy storage performance of dielectric capacitor, a large recoverable energy density could be derived by introducing a slim polarization-electric field hysteresis loop into dielectric materials by various technical approaches. Many research teams have explored various dielectric capacitor technologies to demonstrate high output power density and ultrafast charging/discharging behavior. This article reviews the recent research progress in high-performance dielectric capacitors for pulsed-power electronic applications.

• Microbiology and Biotechnology Letters
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• v.28 no.1
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• pp.26-32
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• 2000

Electrostatic forces contribute to the high degree of enzyme transition state complementarity in enzyme catalyzed reaction and such forces are modified by the solvent through its dielectric constant and polar properties. The contributions of electrostatic interaction to the formation of ES complex and the stabilization of transition state of the trypsin catalyzed reaction were probed by kinetic studied with high pressure and solvent dielectric constant. A good correlation has been observed between the increase of catalytic efficiency of trypsin and the decrease of solvent dielectric constant. Activation volume linearly decreased as the dielectric constant of solvent decreased, which means the increase in the reaction rae. Moreover, the decrease of activation volume by lowering the solvent dielectric constant implies a solvent penetration of the active with and a reduction of electrostatic energy for the formation of dipole of the active site oxyanion hole. When the 야electric constant of the solvents was lowered to 4.7 unit, the loss of activation energy and that of free energy of activation were 2.262 KJ/mol and 3.169 KJ/mol, respectively. The results of this study indicate that the high pressure kinetics combined with solvent effects can provide unique information on enzyme reaction mechanisms, and the controlling the solvent dielectric constant can stabilize the transition state of the trypsin-catalyzed reaction.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.1
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• pp.80-84
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• 2014

The discharge characteristics of Surface Dielectric Barrier Discharge (SDBD) reactor are investigated to find optimal driving condition with adjusting various parameter. When the high voltage with sine wave form is applied to SDBD source, successive pulsed current waveforms are observed owing to multiple ignitions through the long discharge channel and wall charge accumulation on the dielectric surface. The discharge voltage, total charge between dielectrics, mean energy and power are calculated from measured current and voltage according to electrode gap and dielectric thickness. Discharge mode transition from filamentary to diffusive glow is observed for narrow gap and high applied voltage case. However, when the diffusive discharge is occurred with high applied voltage, the actual firing voltage is always lower than that with low driving voltage. The $Si_3N_4$, $MgF_2$, $Al_2O_3$ and $TiO_2$ are considered for dielectric protection and high secondary electron emission coefficient. SDBD with $MgF_2$ shows the lowest breakdown voltage. $MgF_2$ thin film is proposed as a protection layer for low voltage atmospheric dielectric barrier discharge devices.

• Journal of the Korea Institute of Military Science and Technology
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• v.10 no.3
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• pp.114-119
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• 2007

Dielectric properties of quartz glass and $Si_3N_4$ are investigated using the waveguide method from room temperature to $800^{\circ}C$. For the case of dielectric constant, $Si_3N_4$ showed similar increase with quartz glass up to $300^{\circ}C$, but less increase from $300^{\circ}C$ to $800^{\circ}C$. For the case of loss tangent, those showed gradual increase with temperature except of some temperature points. The loss tangent of $Si_3N_4$ and quartz glass increased up to 18.2% and 12.5% respectively. Through these researches, high temperature dielectric properties of silicon nitride materials are characterized.

• Journal of Sensor Science and Technology
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• v.29 no.1
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• pp.7-13
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• 2020

Dielectric capacitors are integral components in electronic devices that protect the electric circuit by providing modulated steady voltage. Explosive growth of the electric automobile market has resulted in an increasing demand for dielectric capacitors that can operate at temperatures as high as 400 ℃. To surpass the operation temperature limit of currently available commercial capacitors that operate in temperatures up to 125 ℃, Bi_1/2Na_1/2TiO₃ (BNT), which has a large temperature-insensitive dielectric response with a maximum dielectric permittivity temperature of 300 ℃, was selected. By introducing an intentional A-site cation deficiency and post-heat treatment, we successfully manage to control the dielectric properties of BNT to use it for high-temperature applications. The key feature of this new BNT is remarkable reduction in dielectric loss (0.36 to 0.018) at high temperature (300 ℃). Structural, dielectric, and electrical properties of this newly developed BNT were systematically investigated to understand the underlying mechanism.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.15-24
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• 2000

The dielectric relaxation of high-dielectric capacitors could be understood as a dynamic property of the capacitor in the time domain, which is regarded as a primarily important charge loss mechanism during the refresh time of DRAMs. Therefore, the equivalent circuit of the dielectric relaxation of the high-dielectric capacitor is essentially required to investigate its effects on DRAM. Nevertheless, There is not any theoretical method which is generally applied to realize the equivalent circuit of the dielectric relaxation. Recently, we have developed a novel procedure for the circuit modeling of the dielectric relaxation of high-dielectric capacitor utilizing the frequency domain. This procedure is a general method based on theoretical approach. We have also verified the feasibility of this procedure through experimental process. Finally, we successfully investigated the effect of dielectric relaxation on DRAM operation with the obtained equivalent circuit through this new method.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.3
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• pp.31-36
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• 2001

Dielectric material which is suitably designed for the application of the high-temperature electrostatic chucks(HTESCS) has been developed. Electrical resistivities and dielectric constants of the dielectric layer satisfy the demands for the proper operation of HTESC, and coefficient of thermal expansion(CTE) of the dielectric material matches well that of the bottom insulator so that it secures stable structure. In order to minimize particle contaminations, borosilicate glass(BSG) is selected as a bonding layer between dielectric layer and bottom insulator, and silver is used as a electrode. BSG is solidly bonded between upper dielectric and bottom insulator, and no diffusions or reactions are observed among silver electrode, dielectric, and glass layers. The chucking characteristics of the fabricated HTESC are found to be superior to those of the commercialized one.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.8
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• pp.685-689
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• 2005

In the fabrication and design of MLCCs (Multilayer Ceramic Capacitors) with Ni inner electrode for medium and high voltage, reliability and dielectric breakdown mode have been investigated. For thickness of green sheet, the relationship between the rated voltage versus the thickness of green sheet. Increasing the thickness of green sheet increases the dielectric breakdown voltage. However, a practical limit to this linear relationship occurs at 30 urn and above. As the thickness of green sheet increased, dielectric breakdown voltage and weibull coefficient is increased, but abruptly decrease at 30 urn and 36 urn. When 24 urn of green sheet thickness, weibull coefficient and dielectric breakdown voltage were 13.58 and 70 V/um respectively. The results enabling the MLCCs to demonstrate high levels of reliability at medium and high voltage.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.463-463
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• 2012

ITRS (international technology roadmap for semiconductors)에 따르면 MOS(metal-oxide-semiconductor)의 CD (critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/$SiO_2$를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두된다고 보고하고 있다. 일반적으로 high-k dielectric를 식각시 anisotropic 한 식각 형상을 형성시키기 위해서 plasma를 이용한 RIE (reactive ion etching)를 사용하고 있지만 PIDs (plasma induced damages)의 하나인 PIED (plasma induced edge damage)의 발생이 문제가 되고 있다. PIED의 원인으로 plasma의 direct interaction을 발생시켜 gate oxide의 edge에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 high-k dielectric의 식각공정에 HDP (high density plasma)의 ICP (inductively coupled plasma) source를 이용한 원자층 식각 장비를 사용하여 PIED를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. One-monolayer 식각을 위한 1 cycle의 원자층 식각은 총 4 steps으로 구성 되어 있다. 첫 번째 step은 Langmuir isotherm에 의하여 표면에 highly reactant atoms이나 molecules을 chemically adsorption을 시킨다. 두 번째 step은 purge 시킨다. 세 번째 step은 ion source를 이용하여 발생시킨 Ar low energetic beam으로 표면에 chemically adsorbed compounds를 desorption 시킨다. 네 번째 step은 purge 시킨다. 결과적으로 self limited 한 식각이 이루어짐을 볼 수 있었다. 실제 공정을 MOS의 high-k dielectric에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU (North Carolina State University) CVC model로 구한 EOT (equivalent oxide thickness)는 변화가 없으면서 mos parameter인 Ion/Ioff ratio의 증가를 볼 수 있었다. 그 원인으로 XPS (X-ray photoelectron spectroscopy)로 gate oxide의 atomic percentage의 분석 결과 식각 중 발생하는 gate oxide의 edge에 trap의 감소로 기인함을 확인할 수 있었다.