• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.118-118
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• 2011

The Nano-Floating Gate Memory(NFGM) devices with ZnO:Cu thin film embedded in Al2O3 and AlOx-SAOL were fabricated and the electrical characteristics were evaluated. To further improve the scaling and to increase the program/erase speed, the high-k dielectric with a large barrier height such as Al2O3 can also act alternatively as a blocking layer for high-speed flash memory device application. The Al2O3 layer and AlOx-SAOL were deposited by MLD system and ZnO:Cu films were deposited by ALD system. The tunneling layer which is consisted of AlOx-SAOL were sequentially deposited at $100^{\circ}C$. The floating gate is consisted of ZnO films, which are doped with copper. The floating gate of ZnO:Cu films was used for charge trap. The same as tunneling layer, floating gate were sequentially deposited at $100^{\circ}C$. By using ALD process, we could control the proportion of Cu doping in charge trap layer and observe the memory characteristic of Cu doping ratio. Also, we could control and observe the memory property which is followed by tunneling layer thickness. The thickness of ZnO:Cu films was measured by Transmission Electron Microscopy. XPS analysis was performed to determine the composition of the ZnO:Cu film deposited by ALD process. A significant threshold voltage shift of fabricated floating gate memory devices was obtained due to the charging effects of ZnO:Cu films and the memory windows was about 13V. The feasibility of ZnO:Cu films deposited between Al2O3 and AlOx-SAOL for NFGM device application was also showed. We applied our ZnO:Cu memory to thin film transistor and evaluate the electrical property. The structure of our memory thin film transistor is consisted of all organic-inorganic hybrid structure. Then, we expect that our film could be applied to high-performance flexible device.----못찾겠음......

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.818-824
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• 2006

The effects of high-temperature process required to fabricate the SiC devices on the surface morphology and the electrical characteristics were investigated for 4H-SiC Schottky diodes. The 4H-SiC diodes without a graphite cap layer as a protection layer showed catastrophic increase in an excess current at a forward bias and a leakage current at a reverse bias after high-temperature annealing process. Moreover it seemed to deviate from the conventional Schottky characteristics and to operate as an ohmic contact at the low bias regime. However, the 4H-SiC diodes with the graphite cap still exhibited their good electrical characteristics in spite of a slight increase in the leakage current. Therefore, we found that the graphite cap layer serves well as the protection layer of silicon carbide surface during high-temperature annealing. Based on a closer analysis on electric characteristics, a conductive surface transfiguration layer was suspected to form on the surface of diodes without the graphite cap layer during high-temperature annealing. After removing the surface transfiguration layer using ICP-RIE, Schottky diode without the graphite cap layer and having poor electrical characteristics showed a dramatic improvement in its characteristics including the ideality factor[${\eta}$] of 1.23, the schottky barrier height[${\Phi}$] of 1.39 eV, and the leakage current of $7.75\{times}10^{-8}\;A/cm^{2}$ at the reverse bias of -10 V.

• Fire Science and Engineering
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• v.33 no.4
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• pp.121-129
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• 2019

The Chemical Control Act of 2015 was enhanced to ensure the safe management of hazardous chemicals. In particular, there have been substantial changes in the standards for the installation and management of handling facilities for manufacturing and storing hazardous chemicals. However, some standards for handling facilities are difficult to implement due to a lack of physical space or because of safety accidents during facility improvements. Therefore, the Safety assessment system (SAS) has been operating for such facilities since 2018. This study developed a leakage trajectory evaluation module that can easily evaluate the outside of a dike for safety evaluation. We analyzed two case studies on a dike for hydrochloric acid and sulfuric acid storage tanks with this module and suggest a reasonable plan for the facility. We believe that it will be possible to more easily submit SAS reports at chemical plants by using this evaluation module. This study is expected to contribute to the improvement of the safety design of hazardous chemical handling facilities.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.04b
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• pp.14-16
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• 2008

Built-in voltage in organic light-emitting diodes was studied using modulated photocurrent technique ambient conditions. From the bias voltage-dependent photocurrent, built-in voltage of the device is determined. The applied bias voltage when the magnitude of modulated photocurrent is zero corresponds to a built-in voltage. Built-in voltage in the device is generated due to a difference of work function of the anode and cathode. A device was made with a structure of anode/$Alq_3$/cathode to study a built-in voltage. ITO was used as an anode, and Al and LiAl were used as a cathode. A layer thickness of Al and LiAl were 100nm. Obtained built-in voltage is about 1.0V in the Al layer was used as a cathode. The obatined built-in voltage is about 1.6V in the LiAl layer was used as a cathode. The result of built-in voltage is dependent of cathode. We can see that the built-in voltage increase up to 0.4V when the LiAl layer was used as the cathode. These results correspond to the work function of LiAl which is lower than that of Al. As a result, the barrier height for an electron injection from the cathode to the organic layer could be lowered when the LiAl was used as a cathode.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.291.1-291.1
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• 2016

Graphene by one of the two-dimensional (2D) materials has been focused on electronic applications due to its ultrahigh carrier mobility, outstanding thermal conductivity and superior optical properties. Although graphene has many remarkable properties, graphene devices have low on/off current ratio due to its zero bandgap. Despite considerable efforts to open its bandgap, it's hard to obtain appropriate improvements. To solve this problem, heterojunction barristor was proposed based on graphene. Mostly, this heterojunction barristor is made by transition metal dichalcogenides (TMDs), such as molybdenum disulfide ($MoS_2$) and tungsten diselenide ($WSe_2$), which have extremely thickness scalability of TMDs. The heterojunction barristor has the advantage of controlling graphene's Fermi level by applying gate bias, resulting in barrier height modulation between graphene interface and semiconductor. However, charged impurities between graphene and $SiO_2$ cause unexpected p-type doping of graphene. The graphene's Fermi level modulation is expected to be reduced due to this p-doping effect. Charged impurities make carrier mobility in graphene reduced and modulation of graphene's Fermi level limited. In this paper, we investigated theoretically and experimentally a relevance between graphene's Fermi level and p-type doping. Theoretically, when Fermi level is placed at the Dirac point, larger graphene's Fermi level modulation was calculated between -20 V and +20 V of $V_{GS}$. On the contrary, graphene's Fermi level modulation was 0.11 eV when Fermi level is far away from the Dirac point in the same range. Then, we produced two types heterojunction barristors which made by p-type doped graphene and graphene treated 2.4% APTES, respectively. On/off current ratio (32-fold) of graphene treated 2.4% APTES was improved in comparison with p-type doped graphene.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.1
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• pp.22-28
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• 2009

We investigated the sintering and electric properties of ZnO-1.0 at% $TeO_2$ (ZT1) and 1.0 at% Mn-doped ZT1(ZT1M1) system. $TeO_2$ itself melts at $732^{\circ}C$ in air but forms the $ZnTeO_3$ or $Zn_2Te_3O_8$ phase with ZnO as increasing temperature and therefore retards the densification of ZnO to $1000^{\circ}C$. In ZT1M1 system, also, the densification of ZnO was retarded up to $1000^{\circ}C$ and then reached > 90% of theoretical density above $1100^{\circ}C$. It was found that a good varistor characteristics(nonlinear coefficient $a{\sim}60$) were developed in ZT1M1 system sintered at $1100^{\circ}C$ due to Mn which known as improving the nonlinearity of ZnO varistors. The results of C-V characteristics such as barrier height (${\Phi}_b$), donor density ($N_D$), depletion layer (W), and interface state density ($N_t$) in ZT1M1 ceramics were $1.8{\times}10^{17}cm^{-3}$, 1.6 V, 93 nm, and $1.7{\times}10^{12}cm^{-2}$, respectively. Also we measured the resistance and capacitance of grain boundaries with temperature using impedance and electric modulus spectroscopy. It will be discussed about the stability and homogeneity of grain boundaries using distribution parameter ($\alpha$) simulated with the Z(T)"-logf plots.

• Journal of Sensor Science and Technology
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• v.14 no.2
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• pp.96-100
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• 2005

The planar Schottky diodes were fabricated and modeled to probe the device applicability of the cracked GaN epitaxial layer on a (111) silicon substrate. On the unintentionally n-doped GaN grown on silicon, we deposited Ti/Al/Ni/Au as the ohmic metal and Pt as the Schottky metal. The ohmic contact achieved a minimum contact resistivity of $5.51{\times}10.5{\Omega}{\cdot}cm^{2}$ after annealing in an $N_{2}$ ambient at $700^{\circ}C$ for 30 sec. The fabricated Schottky diode exhibited the barrier height of 0.7 eV and the ideality factor was 2.4, which are significantly lower than those parameters of crack free one. But in photoresponse measurement, the diode showed the peak responsivity of 0.097 A/W at 300 nm, the cutoff at 360 nm, and UV/visible rejection ratio of about $10^{2}$. The SPICE(Simulation Program with Integrated Circuit Emphasis) simulation with a proposed model, which was composed with one Pt/GaN diode and three parasitic diodes, showed good agreement with the experiment.

• Journal of IKEEE
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• v.18 no.4
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• pp.447-455
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• 2014

In this research, n-based 4H-MOS Capacitor was fabricated with PECVD (plasma enhanced chemical vapor deposition) process for improving SiC/$SiO_2$ interface properties known as main problem of 4H-SiC MOSFET. To overcome the problems of dry oxidation process such as lower growth rate, high interface trap density and low critical electric field of $SiO_2$, PECVD and NO annealing processes are used to MOS Capacitor fabrication. After fabrication, MOS Capacitor's interface properties were measured and evaluated by hi-lo C-V measure, I-V measure and SIMS. As a result of comparing the interface properties with the dry oxidation case, improved interface and oxide properties such as 20% reduced flatband voltage shift, 25% reduced effective oxide charge density, increased oxide breakdown field of 8MV/cm and best effective barrier height of 1.57eV, 69.05% reduced interface trap density in the range of 0.375~0.495eV under the conduction band are observed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.1
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• pp.229-234
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• 1999

We analyzed the reliability characteristics in platinum schottky diodes with variations of n-type silicon substrates concentrations and temperature variations of measurements. The parameters of reliability measurement analysis are saturation current. turn-on voltage and ideality factor in the forward bias, the breakdown voltage in the reverse bias with device shapes. The shape of devices are square type and long rectangular type for edge effect. As a result, we analyzed that the forward turn-on voltage, barrier height, dynamic resistance and reverse breakdown voltage were decreased but ideality factor and saturation current were increased by increased concentration in platinum and n-silicon junction parts. In measurement temperature(RT, $50^{\circ}C$, $75^{\circ}C$), the extracted electrical parameter values of reliability characteristics were increased at the higher temperature under the forward and reverse bias. The long rectangular type devices were more decreased than the square type in reverse breakdown voltage by tunneling effects of edge part.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.1
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• pp.48-56
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• 1998

Pr\ulcornerO\ulcorner-based ZnO varistors were fabricated in the range of $Y_2$O$_3$additive content from 0.5 to 4.0mol%, and its microstructure and electrical properties were investigated. Yttrium was distributed nearly in the grain boundaries and the cluster phase formed at nodal point but more in cluster phase. The average grain size was decreased markedly from 34.9 to 8.6${\mu}{\textrm}{m}$ with increasing $Y_2$O$_3$additive content. It is believed that the decrease of grain size is attributed to the formation of cluster phase and the weakening of driving force for liquid sintering. As a result, $Y_2$O$_3$was acted as the inhibitor of the grain growth. With increasing $Y_2$O$_3$additive content, the varistor voltage, the activation energy, and the nonlinear exponent increased whereas the leakage current decreased, especially 4.0mol% $Y_2$O$_3$-added varistor exhibited very good I-V characteristics; nonlinear exponent 87.42 and leakage current 46.77nA. On the other hand, as $Y_2$O$_3$additive content increases, the varistor showed tendency of the salient decrease for donor concentration and the increase for barrier height. Conclusively, it is estimated that ZnO:Pr varistor compositions added more than 2.0mol% $Y_2$O$_3$are to be used to fabricate useful varistors.