• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.459-464
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• 2013

A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.71-73
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• 2019

The output current of the Grid Connected Inverter (GCI) can be polluted with harmonics mainly due to i) dead time in switches, ii) non-linearity of switches, iii) grid harmonics, and iv) DC link fluctuation. Therefore, it is essential to design the robust Harmonic Compensation (HC) technique for the improvement of output current quality and fulfill the IEEE 1547 Total harmonics Distortion (THD) limit i.e. <5%. The conventional harmonic techniques often are complex in implementation due to their i) additional hardware needs, ii) complex structure, iii) difficulty in tuning of parameters, iv) current controller compatibility issues, and v) higher computational burden. In this paper, to eliminate the harmonics from the GCI output current, a novel Digital Lock-In Amplifier (DLA) based harmonic detection is proposed. The advantage of DLA is that it extracts the harmonic information accurately, which is further compensated by means of PI controller in feed forward manner. Moreover, the proposed HC method does not require additional hardware and it works with any current controller reference frame. To show the effectiveness of the proposed HC method a 5kW GCI prototype built in laboratory. The output current THD is achieved less than 5% even with 10% load, which is verified by simulation and experiment.

• Journal of the Korean Society for Nondestructive Testing
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• v.35 no.6
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• pp.398-406
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• 2015

This paper explored the results of experimental investigation on carbon fiber reinforced polymer (CFRP) composite sample with thermal wave technique. The thermal wave technique combines the advantages of both conventional thermal wave measurement and thermography using a commercial Infrared camera. The sample comprises the artificial inclusions of foreign material to simulate defects of different shape and size at different depths. Lock-in thermography is employed for the detection of defects. The temperature field of the front surface of sample was observed and analysed at several excitation frequencies ranging from 0.562 Hz down to 0.032 Hz. Four-point methodology was applied to extract the amplitude and phase of thermal wave's harmonic component. The phase images are analyzed to find qualitative and quantitative information about the defects.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.268-269
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• 2017

This paper presents an improved current control strategy for a three-phase grid-connected inverter under distorted grid conditions. Distorted grid condition is undesirable due to negative effects such as power losses and heating problem in electrical equipments. To enhance the power quality of distributed generation systems under such a condition, a modulated finite control set - model predictive control (MFCS-MPC) scheme will be proposed, in which the optimal switching signals of inverter are chosen by online basis using the principle of current error minimization. In addition, the moving average filter (MAF) is used to improve the phase-lock loop in order to obtain the harmonic-free reference currents on the stationary frame. The usefulness of the proposed MFCS-MPC method is proved by the comparative simulation results under different operating conditions.

• Wind and Structures
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• v.20 no.2
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• pp.349-361
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• 2015

Higher-mode vertical vortex-induced vibrations (VIV) have been observed on several steel box-girder suspension bridges where different vertical modes are selectively excited in turn with wind velocity in accordance with the Strouhal law. Understanding the relationship of VIV amplitudes for different modes of vibration is very important for wind-resistant design of long-span box-girder suspension bridges. In this study, the basic rectangular cross-section with side ratio of B/D=6 is used to investigate the effect of different modes on VIV amplitudes by section model tests. The section model is flexibly mounted in wind tunnel with a variety of spring constants for simulating different modes of vibration and the non-dimensional vertical amplitudes are determined as a function of reduced velocity U/fD. Two 'lock-in' ranges are observed at the same onset reduced velocities of approximately 4.8 and 9.4 for all cases. The second 'lock-in' range, which is induced by the conventional vortex shedding, consistently gives larger responses than the first one and the Sc-normalized maximum non-dimensional responses are almost the same for different spring constants. The first 'lock-in' range where the vibration frequency is approximately two times the vortex shedding frequency is probably a result of super-harmonic resonance or the "frequency demultiplication". The main conclusion drawn from the section model study, central to the higher-mode VIV of suspension bridges, is that the VIV amplitude for different modes is the same provided that the Sc number for these modes is identical.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.74-84
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• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.8
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• pp.88-95
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• 2006

This paper proposes an analog type Active Power Filter that adapts to the frequency change of a distributed power supply system. The proposed system removes the harmonic currents in the source power by injecting a compensation current that has the same frequency, 180 degree out of phase with the harmonic currents generated by the load. The detection of the harmonics in the source power for creating the compensating current is realized by a PLL(Phase Lock Loop) and a VCGIC(Voltage Controlled Generalized Impedance Converter). The operation of the proposed system is verified by simulation and experiment.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.5
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• pp.466-476
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• 2011

In this paper, a high-performance current control for the single-phase PWM converter under distorted source voltages is proposed using a composite observer. By applying the composite observer, the fundamental and high-order harmonic components of the source voltage and current are extracted without a delay. The extracted fundamental component is used for a phase-lock loop (PLL) system to detect the phase angle of the source voltage. A multi-PR (proportional-resonant) controller is employed to regulate the single-phase line current. The high-order harmonic components of the line current are easily eliminated, resulting in the sinusoidal line current. The simulation and experimental results have verified the validity of the proposed method.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.77-80
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• 2003

We design the local oscillator system of the 100 GHz band radio receiving system for a cosmic radio observation. We use the YIG oscillator with digital driver which is the main oscillator. This oscillator has a good frequency and phase stability at some temperature variation, and the easy computer aided control characteristics. This total system designed to two subsystem, first is the oscillator system include YIG oscillator, tripler, harmonic mixer and triplexer etc., second is the PLL system to supply the precise and stable local oscillator frequency to mixer. The proposed local oscillator system in this paper can be use a single or multi pixel receiver because this system can be lock the local oscillator frequency automatically using PC.

• Journal of Astronomy and Space Sciences
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• v.20 no.3
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• pp.185-196
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• 2003

In this paper, we make a design study for a local oscillator system of the 100 ㎓ band cosmic radio receiving system. We use the YIG oscillator with digital driver which is the main oscillator. This oscillator has a good frequency and phase stability at some temperature variation, and the easy computer aided control characteristics. This total system designed to two subsystem, first is the oscillator system include YIG oscillator, tripler, harmonic mixer and triplexer etc., second is the PLL system to supply the precise and stable local oscillator frequency to mixer. The proposed local oscillator system in this paper can be used in a single or multi pixel receiver because this system can be lock the local oscillator frequency automatically using PC.