• Journal of Advanced Marine Engineering and Technology
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• v.40 no.6
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• pp.542-547
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• 2016

In recent times, Internet of Things (IoT) has attracted wide attention, and there are increasing requests for IoT application services. Open-Source Hardware (OSH) utilizes a variety of components that are created through the sharing of hardware design so that others developers can also work on it. The concept of "open source" that attracted attention in the software industry has been applied to the hardware field by the emergence of IoT market. The emergence of OSH that has the advantage of low hardware cost and faster development encourages the idea of a diverse IoT application services. In this paper, we describe an IoT application service system that is developed using the OSH platform Arduino and Raspberry Pi to process collection, exchange, and computation of the environmental information. The overall system architecture and hardware and software components are presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.518-525
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• 2003

In this paper, we present a fast hardware architecture to implement a parallel 2-dimensional discrete wavelet transform(DWT)based on the lifting scheme DWT framework. The conventional 2-D DWT had a long initial and total latencies to get the final 2D transformed coefficients because the DWT used an entire input data set for the transformation and transformed sequentially The proposed architecture increased the parallel performance at computing the row directional transform using new data splitting method. And, we used the hardware resource sharing architecture for improving the total throughput of 2D DWT. Finally, we proposed a scheduling of hardware resource which is optimized to the proposed hardware architecture and splitting method. Due to the use of the proposed architecture, the parallel computing efficiency is increased. This architecture shows the initial and total latencies are improved by 50% and 66%.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.4
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• pp.231-239
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• 2007

This paper presents the trade-off relationship between area and performance in the hardware design space exploration for the Korean national standard 128-bit block cipher algorithm SEED. In this paper, we compare the following four hardware design types of SEED algorithm : (1) Design 1 that is 16 round fully pipelining approach, (2) Design 2 that is a one round looping approach, (3) Design 3 that is a G function sharing and looping approach, and (4) Design 4 that is one round with internal 3 stage pipelining approach. The Design 1, Design 2, and Design 3 are the existing design approaches while the Design 4 is the newly proposed design in this paper. Our new design employs the pipeline between three G-functions and adders consisting of a F function, which results in the less area requirement than Design 2 and achieves the higher performance than Design 2 and Design 3 due to pipelining and module sharing techniques. We design and implement all the comparing four approaches with real hardware targeting FPGA for the purpose of exact performance and area analysis. The experimental results show that Design 4 has the highest performance except Design 1 which pursues very aggressive parallelism at the expanse of area. Our proposed design (Design 4) shows the best throughput/area ratio among all the alternatives by 2.8 times. Therefore, our new design for SEED is the most efficient design comparing with the existing designs.

• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.6
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• pp.303-309
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• 2013

Cloud storage services are used for efficient sharing or synchronizing of user's data across multiple mobile devices. Although cloud storages provide flexibility and scalability in storing data, security issues should be handled. Currently, typical cloud storage services offer data encryption for security purpose but we think such method is not secure enough because managing encryption keys by software and identifying users by simple ID and password are main defectives of current cloud storage services. We propose a secure data access method to cloud storage in mobile environment. Our framework supports hardware-based key management, attestation on the client software integrity, and secure key sharing across the multiple devices. We implemented our prototype using ARM TrustZone and TPM Emulator which is running on secure world of the TrustZone environment.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.196-204
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• 1996

This paper presents a new scheduling algorithm, which is the most improtant subtask in the high level synthesis. The proposed algorithm performs scheduling in consideration of resource sharing concept based on characteristics of conditionsla bransches in the intermediate data structure. CDFG (control data flow graph) generated by a VHDL analyzer. This algorithm constructs a conditon graph based on time frame of each operation using both the ASAP and the ALAP scheduling algorithm. The conditon priority is obtained from the condition graph constructed from each conditional brance. The determined condition priority implies the sequential order of transforming the CDFG with conditonal branches into the CDFG without conditional branches. To minimize resource cost, the CDFG with conditional branches are transformed into the CDFG without conditonal brancehs according to the condition priority. Considering the data dependency, the hardware constraints, and the data execution time constraints, each operation in the transformed CDFG is assigned ot control steps. Such assigning of unscheduled operations into contorl steps implies the performance of the scheduling in the consecutive movement of operations. The effectiveness of this algorithm is hsown by the experiment for the benchmark circuits.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.339-340
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• 2006

In this paper, a low-power deblocking filter structure for H.264 video coding algorithm is proposed. By sharing addition hardware for common filter coefficients, we have designed an efficient deblocking filter structure. Proposed deblocking filter utilizes MUX and DEMUX circuits for input data sharing and shows 44.2% reduction for add operation. In the HDL coding simulation and FPGA implementation, we achieved 19.5% and 19.4% gate count reduction, respectively, comparison with the conventional deblocking filter structure.

• Proceedings of the Earthquake Engineering Society of Korea Conference
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• 2006.03a
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• pp.563-570
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• 2006

Distributed control architecture is based on sharing control and data between multiple nodes on a network Communication and task sharing can be distributed between multiple control computers. Although many communication protocols exist, such as TCP/IP and UDP, they do not have the determinism that realtime control demands. Fiber-optic reflective shared memory creates the opportunity for realtime distributed control. This architecture allows control and computational tasks to be divided between multiple systems and operate in a deterministic realtime environment. One such shared memory architecture is based on Curtiss-Wright ScramNET family of fiber-optic reflective memory. MTS has built seismic and structural control software and hardware capable of utilizing ScramNET shared memory, opening up infinite possibilities in research and new capabilities in Hybrid and Model-In-The-Loop control.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.465-472
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• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.183-186
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• 2002

In this paper, we present an area-efficient programmable FIR digital filter using canonic signed-digit(CSD) coefficients, in which the number of effective nonzero bits of each filter coefficient is reduced by sharing the shift and add logics for common nonzero bits between adjacent coefficients. Also, unused shift and add logics for a low- magnitude coefficient are reassigned to an appropriate high - amplitude coefficient. In consequence, the proposed architecture reduces the hardware area of a programmable FIR filter by about 24% and improves performance about 6-7dB compared to other multiplierless FIR filters with powers-of-two coefficients.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.1
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• pp.107-113
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• 2001

This paper describes dynamic performance analysis of a STATCOM based on 3-level inverter. Major attention is focused on the controller design for 3-level inverter, including regulator design for voltage sharing across the dc link capacitors. A detailed simulation model was developed with Matlab and a scaled hardware model was built and tested to verify the proposed approach. Both simulation and experimental results confirm that the developed controller can regulate the reactive power. The developed controller could be effectively applied to the actual hardware system for STATCOM.