• International Journal of Fuzzy Logic and Intelligent Systems
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• v.13 no.4
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• pp.324-335
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• 2013

This article presents the design, control, and implementation of a small quad-rotor system under the practical limitation of being cost effective for private use, such as in the cases of control education or hobbies involving radio-controlled systems. Several practical problems associated with implementing a small quad-rotor system had to be taken into account to satisfy this cost constraint. First, the size was reduced to attain better maneuverability. Second, the main control hardware was limited to an 8-bit processor such as an AVR to reduce cost. Third, the algorithms related to the control and sensing tasks were optimized to be within the computational capabilities of the available processor within one sampling time. A small quad-rotor system was ultimately implemented after satisfying all of the above practical limitations. Experimental studies were conducted to confirm the control performance and the operational abilities of the system.

• Journal of KIISE:Software and Applications
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• v.32 no.1
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• pp.62-73
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• 2005

Evolvable Hardware is the technique that obtains target function by adapting reconfigurable digital' devices to environment in real time using evolutionary computation. It opens the possibility of automatic design of hardware circuits but still has the limitation to produce complex circuits. In this paper, we have analyzed the fitness landscape of evolvable hardware and proposed a speciation technique of evolving diverse individuals simultaneously, proving the efficiency empirically. Also, we show that useful extra functions can be obtained by analyzing diverse circuits from the speciation technique.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1797-1801
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• 2004

In this paper we show the hardware testbed and software simulator of multi function array radar (MFAR). The hardware MFAR is simple and flexible hardware to implement various radar beamforming and detecting algorithms. To overcome the limitation of hardware MFAR, the software simulator is proposed. User can simulate radar under the various environment conditions adjusting the parameter of simulator. User can set environment of radar, such as the location and velocity of target, jammer and the terrain clutter. The radar use various probing pulses and supports two operation mode, surveillance and tracking mode.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10a
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• pp.77-82
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• 1996

This paper is concerned with how to utilize kinematic redundancy to reconstruct the inverse kinematic solution which is not attainable due to hardware limitations. By analyzing the error due to hardware limitations, we are to show that the recoverability of limitation reduces to the solvability of a reconstruction equation under the feasibility condition. It will be next shown that the reconstruction equation is solvable if the configuration is not a joint-limit singularity. The reconstruction method will be proposed based on the geometrical analysis of recoverability of hardware limitations. The method has the feature that no task motion error is induced by the hardware limitations while minimizing a possible null motion error, under the recoverability assumed.

• Korean Journal of Computational Design and Engineering
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• v.8 no.2
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• pp.65-74
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• 2003

For virtual reality, virtual manufacturing system, or simulation based design, we need to visualize very large and complex 3D models which are comprising of very large number of polygons. To overcome the limited hardware performance and to attain smooth realtime visualization, there have been many researches about algorithms which reduce the number of polygons to be processed by graphics hardware. One of these algorithms, occlusion culling is a method of rejecting the objects which are not visible because they are occluded by other objects, and then passing only the visible objects to graphics hardware. Existing occlusion culling algorithms have some shortcomings such as the required long preprocessing time, the limitation of occluder shape, or the need for special hardware implementation. In this study, an efficient occlusion culling algorithm is proposed. The proposed algorithm reads and analyzes Z-buffer of graphics hardware using Microsoft DirectX, and then determines each object's visibility. This proposed algorithm can speed up visualization by reading Z-buffer using DirectX which can access hardware directly compared to OpenGL, by reading only the region to which each object is projected instead of reading the whole Z-Buffer, and the proposed algorithm can perform more exact visibility test by using simplified model instead of using bounding box. For evaluation, the proposed algorithm was applied to very large polygonal models. And smooth realtime visualization was attained.

• Proceedings of the Korea Multimedia Society Conference
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• 1998.04a
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• pp.366-370
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• 1998

One major limitation of the efficiency of parallel computer designs has been the prohibitively high cost of parallel communication between processors and memories. Linear order concentrators can be used to build theoretically optimal interconnection schemes. Current designs call for building superconcentrators from concentrators, then using these to recursively partition the connection streams O(log2N) times to achieve point-to-point routing. Since the superconcentrators each have O(N) hardware complexity but O(log2N) depth, the resulting networks are optimal in hardware, but they are of O(log2N) depth. This pepth is not better than the O(log2N) depth Bitonic sorting networks, which can be implemented on the O(N) shuffle-exchange network with message passing. This paper introduces a new method of constructing networks using linear order concentrators and expanders, which can be used to build interconnection networks with O(log2N) depth as well as O(Nlog2N) hardware cost. (All logarithms are in base 2 throughout paper)

• Journal of Electrical Engineering and Technology
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• v.10 no.5
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• pp.1989-2000
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• 2015

In this paper, digital peak current mode control for single phase H-bridge inverters is developed and implemented. The digital peak current mode control is achieved by directly controlling the PWM signals by cycle-by-cycle current limitation. Unlike the DC-DC converter where the output voltage always remains in the positive region, the output of DC-AC inverter flips from positive to negative region continuously. Therefore, when the inverter operates in negative region, the control should be changed to valley current mode control. Thus, a novel control logic circuit is required for the function and need to be analyzed for the hardware to track the sinusoidal reference in both regions. The problem of sub-harmonic instability which is inherent with peak current mode control is also addressed, and then proposes the digital slope compensation in constant-sloped external ramp to suppress the oscillation. For unipolar PWM switching method, an adaptive slope compensation in digital manner is also proposed. In this paper, the operating principles and design guidelines of the proposed scheme are presented, along with the performance analysis and numerical simulation. Also, a 200W inverter hardware prototype has been implemented for experimental verification of the proposed controller scheme.

• Publications of The Korean Astronomical Society
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• v.31 no.2
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• pp.11-19
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• 2016

This paper presents the results of test observations toward a point source, 4C39.25, for observation modes with various bandwidths and numbers of IF streams in order to examine a reliability of the Daejeon hardware correlator performance for correlating VLBI (Very Long Baseline Interferometry) data obtained with the several observation modes of the KVN (Korean VLBI Network). We used a DiFX software correlator (DiFX) as a reference, for investigating the output visibilities from the Daejeon corelator. It is found that the band shapes of the output visibilities from two correlators are similar to each other and the correlated flux density for each baseline obtained from the Daejeon hardware correlator is lower by 3 - 7% than that from the DiFX. The flux difference is attributed to the limitation of FPGA resources and the difference of fringe rotation algorithm of the Daejeon hardware correlator. The conversion factor, 0.93 ~ 0.97, is proposed for future correlation with the Daejeon hardware correlator.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.393-396
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• 2014

Recently, the internet of things (IoT) has become increasingly attractive in many areas to realize smart worlds. JavaScript has become prevalent for IoT programming because of its familiarity with web programmers. On the other hand, JavaScript does not allow the direct control of IoT hardware due to its language limitation. This paper proposes the IoT software platform for JavaScript programming to resolve the limitation. For proof of concept, the platform based on SpiderMonkey and Raspberry Pi was implemented.

• ETRI Journal
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• v.32 no.1
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• pp.93-101
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• 2010

A true random number generator (TRNG) is widely used to generate secure random numbers for encryption, digital signatures, authentication, and so on in crypto-systems. Since TRNG is vulnerable to environmental changes, a deterministic function is normally used to reduce bias and improve the statistical properties of the TRNG output. In this paper, we propose a linear corrector for secure TRNG. The performance of a linear corrector is bounded by the minimum distance of the corresponding linear error correcting code. However, we show that it is possible to construct a linear corrector overcoming the minimum distance limitation. The proposed linear corrector shows better performance in terms of removing bias in that it can enlarge the acceptable bias range of the raw TRNG output. Moreover, it is possible to efficiently implement this linear corrector using only XOR gates, which must have a suitable hardware size for embedded security systems.