• 한국신재생에너지학회:학술대회논문집
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• 2005.11a
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• pp.665-665
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• 2005

The existing DSP for utility interactive photovoltaic generation system control generally uses floating point process type. Because it is easy to use for number crunching, however, it is too late and too expensive. Fixed point process DSP TMS320F2812, has high control speed and is rather inexpensive. A very complicated real system can be simulated using hardware-in-the-loop (HIL) system in a virtual environment Therefore, HIL system can speed up research and development process with a little effort. Also current DSP for utility interactive photovoltaic generation system adopts floating point process type, which is easy to use for number crunching. However, fixed point process DSF, TMS320F2812, has high control speed and is rather inexpensive. This paper presents more efficient method for MPPT control using TMS320F2812 along with HIL System.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.431-436
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• 1987

In this paper, the development of an One Loop Controller is described. The functions which are built in the One Loop Controller are summarized and the hardware implemention of these functions using 16 bit microprocessor is described. The developed One Loop Controller is applied to DC_Motor based position control system and it's results are given.

• Journal of the Korea Institute of Military Science and Technology
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• v.16 no.2
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• pp.130-137
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• 2013

In this paper, decoupled controller design for Autonomous Underwater Vehicle(AUV) and its simulated performance test results and Hardware In the Loop Simulation(HILS) results are presented. Control system design is done using the PD control scheme. Stability analysis and step response of closed loop system under uncertain parameter condition are also presented. The results of full coupled nonlinear model simulation show the well applicability of the designed controller. From the results of HILS, we can verify performance of real time processing and implemented hardware for AUV.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.209-210
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• 2016

프로토타입 컨버터 구현 시 전압/전류 제어기의 안정성, 제어 알고리즘, 정상적인 게이트 전압 제어가 보장되지 않은 경우 이를 수정하기 위해 사용하는 기존의 Trial and Error 방식은 조정에 많은 시간 및 비용이 소모된다. 본 논문은 이러한 시간적 비용 저감을 위하여 Control Hardware-in-the-Loop Simulation(CHILS)를 이용하여 제어기의 정상 동작 여부와 성능을 실시간으로 검증하는 방법을 제안한다. 이를 위해 LLC 공진형 컨버터를 CHILS로 구현하여, 개발된 DSP 제어기의 성능을 검증하고자 한다. 제안된 실시간 모의시험에서는 LLC 공진형 컨버터를 Matlab/Simulink에서 모델링 하여, 실제 DSP 제어기의 신호를 컨버터 모델에서 입력받아 모의시험장치의 출력 결과를 관찰함으로써 제어기의 동작 특성을 확인하였다.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.339-340
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• 2015

본 논문에서는 HVDC 제어 시스템의 기능 검증을 위해 구축한 RTDS 기반의 HILS(Hardware-In-the Loop Simulation)시스템 및 시험 결과를 소개하였다. MMC 기반 VSC HVDC는 다수의 직렬 연결된 SM(Sub-Module)을 개별 제어해야 하므로 기존의 LCC HVDC 및 2/3-Level 컨버터 기반의 VSC HVDC와 같은 설비들보다 훨씬 더 복잡한 VBE 구조를 가지고 있다. 또한 짧은 시간 내에 정밀한 제어가 가능해야 하므로 높은 제어 정밀도가 요구된다. (주)효성에서는 제어 시스템의 성능 검증을 위해 RTDS 기반의 HILS(Hardware-In-the Loop Simulation)시스템을 구축하였으며, 이를 이용하여 HVDC 제어 시스템의 성능 시험을 수행하였다. 본 논문에서는 구축된 RTDS 기반의 HILS 시스템 및 시험 결과를 소개하였다.

• Bulletin of the Korean Space Science Society
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• 2010.04a
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• pp.31.2-31.2
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• 2010

편대비행 위성이 공동의 임무를 수행하기 위해서는 편대를 이루는 위성의 각기 다른 초기 오차와 다양한 외란 환경에서도 자세 동기화를 이룰 수 있는 기법이 필요하다. 이 연구에서는 편대비행위성의 자세 동기화를 위하여 비선형 시스템에 대한 준최적 제어기법인 SDRE(State-Dependent Riccati Equation)에 기반한 추적 제어기가 사용되었다. 반작용 휠이 포함된 위성의 자세 동역학이 SDRE 추적 제어기를 구성하는데 이용된다. 이를 Leader/Follower 편대비행 시스템에 적용하며, 기준 자세를 추적하는 Leader 위성의 자세를 Follower 위성이 추적하여 자세 동기화를 이룰 수 있다. MATLAB과 SIMULINK를 이용한 수치해석적 시뮬레이션으로 추적 제어기의 성능을 검증하였으며, 이에 대한 실시간 HIL(Hardware-In-the-Loop) 시뮬레이션이 수행되었다. 무중력 환경을 모사하는 에어베어링시스템과 세 개의 반작용 휠을 장착한 자세제어 HILS(Hardware-In-the-Loop Simulator)는 PC104 타입의 임베디드 컴퓨터에서 SIMULINK의 xPC Target을 이용한 실시간 시뮬레이션 환경을 제공하며, 이에 적용되는 SDRE 추적 제어기는 이산화되어 설계되었다. 또한 SDRE 추적 제어기에 대한 안정성을 보장하는 영역이 추정되어 위 추적 제어기가 위성 편대비행에 적합한 자세 동기화 기법임을 보였다.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.535-538
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• 2005

Today, most fixed-wing aircrafts are equipped with the antiskid brake system. It can modulate braking moments in the wheels optimally, when an aircraft is landing. So it can reduce landing distance and increase safeties. The antiskid brake system for an aircraft are mainly composed of braking moment modulators (hydraulic control valves) and brake control unit. In this paper, a Mark IV type - fully digital - brake controller is studied. For the development of its control algorithms, a 5-DOF (Degree of Freedom) aircraft landing model is composed in the form of matlab/simulink model at first. Then, braking moment control algorithms using wheel decelerations and slips are made. The developed algorithms are tested in software simulations using state-flow toolboxes in matlab/simulink model. Also, a real-time simulation systems are made, which use hydraulic brake systems of a real aircraft, pressure control valves and its controller as hardware components of HIL(Hardware In-the-Loop) simulation. Algorithms tested in software simulations are coded into the controller and the real-time landing simulations are made in very severe road conditions. The real-time simulation results are presented.

• Journal of Power Electronics
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• v.11 no.2
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• pp.202-210
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• 2011

Polymer electrolyte membrane (PEM) fuel cell is one of the popular renewable energy sources and widely used in commercial medium power areas from portable electronic devices to electric vehicles. In addition, the increased integration of the PEM fuel cell with power electronics, dynamic loads, and control systems requires accurate electrical models and simulation methods to emulate their electrical behaviors. Advancement in parallel computation techniques, various real-time simulation tools, and smart power hardware have allowed the prototyping of novel apparatus to be investigated in a virtual system under a wide range of realistic conditions repeatedly, safely, and economically. This paper builds up advancements of optimized model constructions for a fuel cell stack system on a real-time simulator in the view points of improving dynamic model accuracy and boosting computation speed. In addition, several considerations for a power hardware-in-the-loop (PHIL) simulation are provided to electrically emulate the PEM fuel cell stack system with power facilities. The effectiveness of the proposed PHIL simulation method developed on Opal RT's RT-Lab Matlab/Simulink based real-time engineering simulator and a programmable power supply is verified using experimental results of the proposed PHIL simulation system with a Ballard Nexa fuel cell stack.

• KEPCO Journal on Electric Power and Energy
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• v.7 no.1
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• pp.101-105
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• 2021

Encouragement of DER from Korean government with several policies boosts DER installation in power system. When the penetration of DER in the grid is getting high, loss of generation with break-away of DER by abnormal grid conditions should be considered, because loss of high generation causes abnormal low frequency and additional operations of protection system. Therefore, KEPCO where is Korean power utility is preparing improvement in regulations for DERs connected to the grid to support abnormal grid conditions such as low and high frequencies or voltages. This is called 'Ride Through' because the requirement is for DER to maintain grid connection during required periods when abnormal grid conditions occur. However, it is not easy to have a test for ride through capability in reality because emulation of abnormal grid conditions is not possible in real power system in operation. Also, it is not easy to have a study on grid effect when ride through capability fails with the same reason. PHILs (Power Hardware In the Loop System) makes it possible to analyze power system and hardware performance at once. Therefore, this paper introduces PHILs test methods and presents verification of ride through capability especially for low voltage grid conditions.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.543-545
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• 2017

This paper describes the SAO hardware architecture design for high performance in-loop filters. SAO is an inner module of in-loop filter, which compensates for information loss caused by block-based image compression and quantization. However, HEVC's SAO requires a high computation time because it performs pixel-unit operations. Therefore, the SAO hardware architecture proposed in this paper is based on a $4{\times}4$ block operation and a 2-stage pipeline structure for high-speed operation. The information generation and offset computation structure for SAO computation is designed in a parallel structure to minimize computation time. The proposed hardware architecture was designed with Verilog HDL and synthesized with TSMC chip process 130nm and 65nm cell library. The proposed hardware design achieved a maximum frequency of 476MHz yielding 163k gates and 312.5MHz yielding 193.6k gates on the 130nm and 65nm processes respectively.