• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.429-432
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• 2000

The new MPEG-4 video coding standard enables content-based functionalities. In order to support the philosophy of the MPEG-4 visual standard, each frame of video sequences should be represented in terms of video object planes (VOP’s). In other words, video objects to be encoded in still pictures or video sequences should be prepared before the encoding process starts. Therefore, it requires a prior decomposition of sequences into VOP’s so that each VOP represents a moving object. A parallel processing system is required an automatic segmentation to be processed in real-time, because an automatic segmentation is time consuming. This paper addresses the parallel processing: system for an automatic segmentation for separating moving object from the background in image sequences. The proposed parallel processing system comprises of processing elements (PE’s) and a multi-access memory system (MAMS). Multi-access memory system is a memory controller to perform parallel memory access with the variety of types: horizontal, vertical, and block access way. In order to realize these ways, a multi-access memory system consists of a memory module selection module, data routing modules, and an address calculation and routing module. The proposed system is simulated and evaluated by the CADENCE Verilog-XL hardware simulation package.

• IE interfaces
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• v.23 no.4
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• pp.349-356
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• 2010

The role of Intelligent Transportation System (ITS) is to efficiently manipulate the traffic flow and reduce the cost in logistics by using the state of the art technologies which combine telecommunication, sensor, and control technology. Especially, the hardware part of ITS is rapidly adapting to the up-to-date techniques in GPS and telematics to provide essential raw data to the controllers. However, the software part of ITS needs more sophisticated techniques to take care of vast amount of on-line data to be analyzed by the controller for their decision makings. In this paper, the authors develop a traffic congestion prediction model based on several different parameters from the sensory data captured in the Vehicle Detection System (VDS). This model uses the neural network technology in analyzing the traffic flow and predicting the traffic congestion in the designated area. This model also validates the results by analyzing the errors between actual traffic data and prediction program.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.5
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• pp.389-394
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• 2015

This paper proposes a series-connected power conversion system that integrates a photovoltaic power conditioner and a charge-balancing circuit. In conventional methods, a photovoltaic power conditioner and a cell-balancing circuit are needed for photovoltaic systems with energy storage devices, which results in a complex configuration and high cost. To overcome these problems, a series-connected DC-DC power conditioning system that integrates a photovoltaic power conditioner with a charge-balancing circuit is proposed. During the generation, the system operates as power conditioner only, whereas it operates as a cell balancing circuit during the rest time. For the analysis, the operating principle of the circuit and the controller design are done by PSIM simulation. For verification, a hardware prototype with 48-W photovoltaic modules has been implemented. Results verified that the modularized photovoltaic power conversion system with a series-connected storage successfully works with the proposed method.

• Journal of Institute of Control, Robotics and Systems
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• v.12 no.6
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• pp.614-620
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• 2006

Today the automobile has been changed from a mechanical system to an electronic control system fly the development of the electronic technology. In the automobile body, most of these electronic control devices are networked and managed fully by the CAN protocol. But, when a network system is overloaded, unexpected transmission delay for relative low priority objects occurs due to the static priority definition of the CAN protocol. To resolve this problem, this paper proposes a dynamic precedence queue mechanism that creates a queue for the low priority object and its relevant objects to be transmitted, which becomes urgent in an overloaded network system to keep the maximum allowable time delay. For the generated queue, the highest priority is assigned to transmit the queued objects within the shortest time. The mechanism is implemented in the logical link layer of CAN, which does not require any modification of the old CAN hardware. Effectiveness of the proposed mechanism is verified by the real experiments with an automobile network system.

• Journal of Institute of Control, Robotics and Systems
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• v.16 no.5
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• pp.489-497
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• 2010

This paper presents the design of hardware platform, which is a test bed for the navigation system and hovering type AUV (Autonomous Underwater Vehicle) under the OCP (Open Control Platform). The developed AUV test bed consists of two hulls, four thrusters, and the navigation system which uses a SBC2440II with IMU (Inertial Measurement Unit). And the SMC (Sliding Mode Control) is chosen for the diving and steering control of the AUV. This paper uses ACE/TAO RTEC (Real-Time Event Channel) as a middleware platform in order to control and communicate in the developed AUV test bed. In this paper, two computers are used and each of them is dedicated for the specific purpose, the first computer is used as the SMC module and the middleware platform for the ACE/TAO RTEC and the second computer is used for the sensor controller. We analyze the performance of the AUV test bed under the OCP.

• Journal of IKEEE
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• v.20 no.3
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• pp.326-329
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• 2016

HEVC CABAC encoder performs binary arithmetic encoding after syntax elements are converted into binary values. Therefore, in HEVC CABAC decoder, binarized syntax elements from binary arithmetic decoder should be de-binarized into original syntax elements in the de-binarizer. In this paper, a HEVC CABAC de-binarizer architecture was proposed and implemented. It consists of a controller that analyzes and merges binarized syntax elements and an engine that converts merged binarized syntax elements into original syntax elements. The designed de-binarizer was described in Verilog HDL and it was synthesized and verified in 0.18um process technology. Its gate count and maximum operating frequency are 3,114 gates and 220 MHz, respectively.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.6
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• pp.628-634
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• 2000

We propose a data coding scheme for reducing' power consumption and ElVII in transmitting a sequence of data from LCD controller to LCD driver. The proposed coding scheme makes use of reducing data transitions in general text image of PC. It can be implemented with a little hardware and applied to the real-time applications of LCD driving system. We have executed computer simulations of the proposed coding scheme and compared the results of the proposed scheme with those produced by the existing coding schemes. The proposed coding scheme, compared to the existing ones, reduces the switching activity significantly in both of text and picture images.

• Journal of Power Electronics
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• v.13 no.3
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• pp.390-399
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• 2013

As a result of the depletion of fossil fuels and environmental contamination, it has become important to use renewable energy. For the stable utilization of renewable energy sources, energy storage devices must be used. In addition, renewable and distributed power sources with energy storage devices must operate stably under grid-connected mode. This paper proposed dynamic response modeling for renewable power generation systems including a charger/discharger with an energy storage device in order to derive a method to guarantee stable operation while fully utilizing the energy from the energy storage device. In this paper, the principle operation and design guidelines of the proposed scheme are presented, along with a performance analysis and simulation results using MATLAB and PSIM. Finally, a hardware prototype of a 1kW power conditioning system with an energy storage device has been implemented for experimental verification of the proposed converter system.

• 한국방재학회:학술대회논문집
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• 2008.02a
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• pp.361-364
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• 2008

The Application Model in Wireless Sensor Networks(WSNs) consist of wireless sensor network based on sensor hardwares which is combined the micro-controller, chipset for wireless communication and sensors, middleware for dealing with data processing and user application for common service. Applications in WSN have been applied for environmental monitoring, smart factory and have concentrated the services based on remote monitoring applications which is difficult to watch the situation by human. In this paper, we described the construction model for applying for the Ubiquitous disaster prevention system and deal with its conformity. The proposed system includes the selecting the wireless sensor hardware, routing technique for u-Disaster Prevention, composition of middleware and web-interface for application services.

• Journal of Power Electronics
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• v.10 no.4
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• pp.412-418
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• 2010

This paper proposes a new algorithm to generate a reference signal for an active power filter using a sliding-window FFT operation to improve the steady-state performance of the active power filter. In the proposed algorithm the sliding-window FFT operation is applied to the load current to generate the reference value for the compensating current. The magnitude and phase-angle for each order of harmonics are respectively averaged for 14 periods. Furthermore, the phase-angle delay for each order of harmonics passing through the controller is corrected in advance to improve the compensation performance. The steady-state and transient performance of the proposed algorithm was verified through computer simulations and experimental work with a hardware prototype. A single-phase active power filter with the proposed algorithm can offer a reduction in THD from 75% to 4% when it is applied to a non-linear load composed of a diode bridge and a RC circuit. The active power filter with the proposed reference generation method shows accurate harmonic compensation performance compared with previously developed methods, in which the THD of source current is higher than 5%.