• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.189-191
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• 2005

This paper proposes an implementation of a line- voltage sensorless three-phase active power filter. The line synchronization for an active power filter does not require any additional hardware. It can be properly operated under various line-voltage variation. Current compensation is done in the time domain allowing fast time response. All control functions are implemented in software using a single-chip microcontroller, thus simplifying the control circuit. It is shown via experimental results that the proposed controller gives good performance for the line-voltage sensorless active power filter.

• Journal of the Ergonomics Society of Korea
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• v.9 no.1
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• pp.3-14
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• 1990

This article develops a cost-effective and accurate measurement system for heart best intervals. The system is composed of an analog to digital (A/D) converter, an IBM personal computer (an 8088 microprocessor, an 8253-5 timer, an 8259A interrupt controller, and memories) and assembler programs for controlling these hardware components. An exponential smoothing algorithm effectively reduced noise effects from A/D converted electrocardiogram (ECG) signals influenced by 60 Hz alternating current (AC). The system can collect 15000 heart beat intervals with an 1/5400 second unit.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.917-920
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• 1993

Various forms of hardware alternatives exist for the implementation of fuzzy logic controllers. In this paper, we describe a systematic framework for realizing fuzzy heuristics on programmable-logic-devices. Our approach is suitable for the automated development of fuzzy logic controllers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.3
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• pp.444-453
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• 1997

This paper presents the prototype design of hardware/software cosynthesis system for pipelined application-specific instruction processors. Taking application programs in VHDL as inputs, the proposed system generates a pipelined instruction-set processor and the instruction sequences running on the generated machine. The design space of datapath and controller is defined by the architectural templates embedded in the system. Generating the intyermediate code adequate for parallelism analysis and extraction, the system converts it into assembly codes. Experimental results show the effectiveness of the proposed system.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.962-964
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• 2003

In this paper, development of portable power interrupt tester to evaluate microprocessor based control circuits for an endurance under abnormal power source. 89C2051 micro-controller is performed to make power interrupt signal, and software controls peripheral hardwares and built-in functions. Experimental results of this study will offer a good application to electronic appliance maker as a test device of hardware and software debugging use.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1113-1124
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel fur the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit of a field synchronized with the A/D converter. The implemented H/W used the 69%(16980) LAB(Logic Array Block) and 9%(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation of 60 fields/sec(30 frames/sec).

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.30-40
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• 2015

For a shunt power quality controller (SPQC) the DC side voltage value which is closely related to the compensation performance is a significant parameter. Buy so far, very little discussion has been conducted on this in a quantitative manner by previous publications. In this paper, a method to design the DC side voltage of SPQC is presented according to the compensation performance in the single-phase system and the three-phase system respectively. First, for the reactive current and the harmonic current compensation, a required minimal value of the DC side voltage with a zero total harmonic distortion (THD) of the source current and a unit power factor is obtained for a typical load, through the equivalent circuit analysis and the Fourier Transform analytical expressions. Second, when the DC side voltage of SPQC is lower than the above-obtained minimal value, the quantitative relationship between the DC side voltage and the THD after compensation is also elaborated using the curve diagram. Hardware experimental results verify the design method.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1392-1395
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• 2004

In order to successfully develop attitude and orbit control subsystem(AOCS), AOCS engineer performs hardware selection, controller design and analysis, control logic and interface verification on electrical test bed, integrated system test, polarity test, and finally verification on orbit after launching. Attitude and orbit control subsystem for KOMPSAT-2 consists of standby mode, sun mode, maneuver mode, science mode, and power safe mode to stabilize and to control the spacecraft for performing the mission. The sun mode is usually divided into sun point submode, earth search submode and safe hold submode. The maneuver mode is divided into attitude hold submode and ${\triangle}$ V submode, while the science mode divided into science coarse submode and science fine submode. Moreover, it is added to back-up mode which uses wheels as an actuator for sun mode and maneuver mode. In this paper, we describe the controller design process and the performance of the design results with respect to the sun mode and the maneuver mode based on thrusters as an actuator using on flexible model.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1539-1543
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• 2004

This paper describes platform overview, system integration and dynamic walking control of the humanoid robot, KHR-2 (KAIST Humanoid Robot - 2). We have developed KHR-2 since 2003. KHR-2 has totally 41 DOF (Degree Of Freedom). Each arm including a hand has 11 DOF and each leg has 6 DOF. Head and trunk also has 6 DOF and 1 DOF respectively. In head, two CCD cameras are used for eye. In order to control all joints, distributed control architecture is adopted to reduce the computation burden of the main controller and to expand the devices easily. The main controller attached its back communicates with sub-controllers in real-time by using CAN (Controller Area Network) protocol. We used Windows XP as its OS (Operating System) for fast development of main control program and easy extension of peripheral devices. And RTX, HAL(Hardware Abstraction Layer) extension program, is used to realize the real-time control in Windows XP environment. We present about real-time control of KHR-2 in Windows XP with RTX and basic walking control algorithm. Details of the KHR-2 are described in this paper.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1684-1688
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• 2003

In this paper, position and speed control algorithm of LSM (Linear Stepping Motor) using general-purpose PCI I/O board is discussed. The main purpose of this paper is to show that LSM controller can be established on the non real time operating system such as Microsoft Win2000 under the assumption that thread priority strategy is well designed. We can guarantee sampling interval less than 5msec based on the Pentium III microprocessor. Therefore this kind of LSM controller development environment makes shorten the prior research period needed to verify the validness of the proposed control strategy. We also introduce the tool of the real-time windows target system of matlab, which also makes shorten the prior research period. The main focus of this paper is on developing general purpose NT device driver which can drive the general purpose PCI board and applying it for implementing the hardware interface for 2- axis linear stepping motor control. From the experimental results show that the developed LSM controller guarantee 2 micrometer resolution in position control with 10cm/sec moving speed