• Title/Summary/Keyword: Hardware Controller

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발사체 추력백터제어 구동장치용 컴퓨터 하드웨어 설계

  • Park, Moon-Su;Lee, Hee-Joong;Min, Byeong-Joo;Choi, Hyung-Don
    • Aerospace Engineering and Technology
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    • v.3 no.2
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    • pp.56-64
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    • 2004
  • In this research, design results of computer hardware which control solid motor movable nozzle thrust vector control(TVC) actuator for Korea Space Launch Vehicle I(KSLV-I) are described. TVC computer hardware is the equipment which has jobs for receiving control commands from Navigation Guidance Unit(NGU) and then actuating TVC actuator. Also, it has ability to communicate with other on board or ground equipments. Computer hardware has a digital signal processor as the main processor which is capable of high speed calculating ability of control algorithm, so it can have more stability, reliability and flexibility than the previous analog controller of KSR-III. Target board was designed for on board program development and then first prototype hardware was developed. Top level system design criteria, hardware configurations and ground support equipment of TVC computer system are described.

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Performance Evaluation on an Active Camera Mount System for UAV via Hardware-in-the-loop-simulation (HILS를 통한 무인항공기 카메라 지지 능동 마운트 시스템의 진동제어 성능 평가)

  • Oh, Jong-Suk;Choi, Seung-Bok;Cho, Han-Jun;Lee, Chul-Hee;Cho, Myeong-Woo
    • Transactions of the Korean Society for Noise and Vibration Engineering
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    • v.20 no.8
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    • pp.767-773
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    • 2010
  • In the present work, vibration control performance of piezoactuator-based active mount system for unmanned aero vehicle(UAV) equipment is evaluated via hardware in the loop simulation(HILS). At first, the vibration level of UAV is measured and from this vibration data, the proper piezostack actuator is selected. Then, the dynamic model of active mount system including four active mounts and UAV camera equipment is derived. In order to evaluate vibration control performance, the HILS system is constructed. The proposed mount is prepared as hardware part and the other mounts are considered in software part. A sliding mode controller is designed and implemented to the HILS system. Effective vibration control results are presented in both time and frequency domains.

COTS Based Air Data Recording System for SmartUAV (상용 기성품에 기반한 스마트무인기 탑재자료저장장치)

  • Chang, Sung-Ho;Kim, Young-Min
    • Aerospace Engineering and Technology
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    • v.9 no.2
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    • pp.153-160
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    • 2010
  • Air Data Recording System (ADRS) is the flight data recorder for the SmartUAV development. ADRS of the low cost designed for the SmartUAV has been developed and tested through the ground test. ADRS is the reconstructing data acquisition system and can be programmed automation controller. This paper focuses on the design aspects of the hardware and software. The hardware aspects of the ADRS include details about the hardware configurations for the interfaces with the Digital Flight Control Computer(DFCC) and sensors, components modifications. The software section describes the ADRS Operating System(OS) and data flow for archived files. Finally, ADRS-based results of the SmartUAV that include the Iron-bird test, system interface test and ground test are presented.

Implementation of a PC based Hardware Simulator with 128 channels (128채널 PC 기반 하드웨어 시뮬레이터 구현)

  • 정갑천;최종현;박성모
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.40 no.5
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    • pp.298-305
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    • 2003
  • This paper describes a 128-channel hardware simulator that is useful for verification and testing of digital circuits. It performs logic analyzer function and signal generator function at the same time. The core module, which implements one channel of the simulator, operates as a controller with independent memory and internal mode. Therefore, we can easily extend the number of channels with addition of core module. Moreover, since the simulator was implemented as a PC based system, one can construct a low-cost system and can configure convenient GUI(Graphic User Interface) environment. The simulator implemented using FPGA operates at 50Mhz and consumes 55W power as average.

Real-Time Hardware Simulator for Grid-Tied PMSG Wind Power System

  • Choy, Young-Do;Han, Byung-Moon;Lee, Jun-Young;Jang, Gil-Soo
    • Journal of Electrical Engineering and Technology
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    • v.6 no.3
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    • pp.375-383
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    • 2011
  • This paper describes a real-time hardware simulator for a grid-tied Permanent Magnet Synchronous Generator (PMSG) wind power system, which consists of an anemometer, a data logger, a motor-generator set with vector drive, and a back-to-back power converter with a digital signal processor (DSP) controller. The anemometer measures real wind speed, and the data is sent to the data logger to calculate the turbine torque. The calculated torque is sent to the vector drive for the induction motor after it is scaled down to the rated simulator power. The motor generates the mechanical power for the PMSG, and the generated electrical power is connected to the grid through a back-to-back converter. The generator-side converter in a back-to-back converter operates in current control mode to track the maximum power point at the given wind speed. The grid-side converter operates to control the direct current link voltage and to correct the power factor. The developed simulator can be used to analyze various mechanical and electrical characteristics of a grid-tied PMSG wind power system. It can also be utilized to educate students or engineers on the operation of grid-tied PMSG wind power system.

FPGA Design of Digital Circuit for TACAN (TACAN을 위한 디지털 회로의 FPGA 구현)

  • Seo, Young-Ho;Choi, Hyun-Jun;Kim, Dong-Wook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.12B
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    • pp.1175-1182
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    • 2010
  • In this paper, we implemented a digital circuit which is targeted on FPGA for estimating azimuth information and distance between aircraft and ground station. All functions for signal processing of TACAN were integrated into a FPGA. The proposed hardware consists of input interface, register file, decoder, signal generator and main controller block. The designed hardware includes a function to generating pulse pair group for azimuth information, a function to responding the interrogation of aircraft for estimating distance between aircraft and ground station, and a function to provide ID information of ground station. The proposed hardware was implemented with FPGA chipset of ALTERA and occupied with 7,071 logic elements.

Design and Verification of the Hardware Architecture for the Active Seat Belt Control System Compliant to ISO 26262 (ISO 26262에 부합한 능동형 안전벨트 제어 시스템의 하드웨어 아키텍처 설계 및 검증)

  • Lee, Jun Hyok;Koag, Hyun Chul;Lee, Kyung-Jung;Ahn, Hyun-Sik
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.65 no.12
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    • pp.2030-2036
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    • 2016
  • This paper presents a hardware development procedure of the ASB(Active Seat Belt) control system to comply with ISO 26262. The ASIL(Automotive Safety Integrity Level) of an ASB system is determined through the HARA(Hazard Analysis and Risk Assessment) and the safety mechanism is applied to meet the reqired ASIL. The hardware architecture of the controller consists of a microcontroller, H-bridge circuits, passive components, and current sensors which are used for the input comparison. The required ASIL for the control systems is shown to be satisfied with the safety mechanism by calculation of the SPFM(Single Point Fault Metric) and the LFM(Latent Fault Metric) for the design circuits.

Control of Active Engine Mount System Featuring MR Fluid and Piezostack via HILS (MR 유체와 압전스택을 이용한 능동 엔진마운트 시스템의 HILS 제어)

  • Lee, Dong-Young;Choi, Seung-Bok
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2009.10a
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    • pp.351-356
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    • 2009
  • This paper presents vibration control performance of active engine mount system installed with the magneto-rheological (MR) mount and the piezostack mount. The performance is evaluated via hardware-in-the-loop-simulation(HILS) method. As a first step, six degrees-of freedom dynamic model of an in-line four-cylinder engine which has three points mounting system is derived by considering the dynamic behaviors of MR mount and piezostack mount. As a second step, sliding mode controller(SMC) is synthesized to actively control the imposed vibration In order to demonstrate the effectiveness of the proposed active engine mount, vibration control performances are evaluated under various engine operating speeds (wide frequency range) using HILS method and presented in time and frequency domain.

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개방형 로봇제어를 위한 표준기준모델에 관한 연구

  • 김호철;홍금식;이석희
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1995.10a
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    • pp.872-875
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    • 1995
  • The strategy of open architecture control system intends to integrate manufacturing components on a single platform, so that a particular component can be easily added and/or replaced. Therefore, the control scheme is neither hardware dependent nor software dependent. In this paper a modular and object oriented approach for the open architecture structure of control systems is invesigated. A standard reference model for genetic manufacturer system, which consists of three modules; hardware module, operating system module, and application software module, is first proposed. Then a standard reference model for open architecture robot control system is suggested.

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ASIC for Ethernet based real_time communication in DCS

  • Nakajima, Takeshi
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.1836-1839
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    • 2005
  • We have developed Ethernet based real-time communication systems called "Vnet/IP" for DCS which is the control system for process automation. This paper describes the features and the technologies of the ASIC which is utilized in the communication interface hardware for Vnet/IP. Vnet/IP has been developed for mission-critical communications. Hence it has real-time feature, high reliability and precise time synchronization capability. At the same time, it is able to deal with standard protocols without influence on mission-critical communications. The communication interface hardware has a host interface and dual redundant network interfaces. The host interface can be chosen PCI-bus or R-bus which is the proprietary internal bus developed for the high reliable redundant controller. Each network interface is a RJ45 connection with 1Gbps maximum in compliance with IEEE802.3.

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