• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.413-416
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• 2004

The tracking antenna system must be always pointed to a satellite for data link among moving vehicles. Especially, for an antenna mounted on a moving vehicle, it needs the stabilized the antenna system. So, software and hardware, signal processing of motion detection sensors, real-time processing of vehicle dynamics, trajectory estimation of satellite, antenna servo mechanism, and tracking algorithm, are unified in the antenna system. The purpose of this paper is to design the embedded tracking antenna control system for satellite communication. The embedded OS(Operating System) based stabilization and tracking algorithm was implemented. The performance of the designed embedded control system was verified by the real satellite communication test.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.160-162
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• 2014

A programmable video decoding system with multi-core DSP and co-processors is presented. This system is adopted by Digital TV SoC (System on Chip) and is used for FHD HEVC (High Efficiency Video Coding) decoder. Using the DSP based programmable solution, we can reduce commercialization period by one year because we can parallelize algorithm development, software optimization and hardware design. In addition to the HEVC decoding, the proposed system can be used for other application such as other video decoding standard for multi-format decoder or video quality enhancement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3154-3164
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• 1996

A major concern in a cellular mobile communication system is how to efficiently utilize the limited amount of frequencies. Various channel assignment methods and traffic sharing schemes have been proposed to improve system performance. However, these approaches suffer from complicated software and hardware requirements due to increased amount of traffic control In this paper, we propose a new method for improving system performance by controlling the powers of the set-up and voice channels of each cell site. We first show that the average number of blocked calls in a system is minimized when the traffic reates are made identical for all cell sites in a system. This result, together with the relationship between the channel powers and the service area, is used to determine the appropriate channel powers of each cell site. We also determine the upper limit on the channel power of each cell site considering co-channel interference and numerically show that the proposed method is effective in reducing the number of blocked calls without an excessive increase in the amount of system control.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.618-619
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• 2013

This paper presents a method of constructing the embedded systems based on hardware/software co-design approach that was key methodology. The proposed method was important technology enable to implement advanced multimedia systems and digital contents creating that are rapidly growing of the new information technology.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.258-258
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• 2004

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.754-766
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• 2010

In the wireless communication protocols, a network device is responsible for the operation of lower-layers. The network device consists of hardware and software modules, so it can be designed using system-on-chip simulator. The simulator design needs the support of a network simulator as well as system-on-chip simulator, because the network device interact with various higher layer communication protocols. Therefore the co-simulator can become a development environment of the network device through the combining of them. In this paper we propose a co-simulator combining these two simulators. The proposed co-simulator does not degrade performance due to integrations. Also, it is easy to integrate them because the implementation of the kernel is independent.

• Journal of Biomedical Engineering Research
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• v.31 no.3
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• pp.187-193
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• 2010

In this study we have designed and fabricated an inexpensive micro electronic system that we call Alvitek. It can indirectly but accurately predict and display the partial pressures of alveolar oxygen and carbon dioxide for the patients in the ICU of a hospital. Alvitek consists of both hardware part and software part. Performance of the system is tested by animal experiment with pigs for various $F_{t}e_{2}$ and RR(Respiratory Rate) values under the mechanical ventilation. The predicted alveolar gas partial pressures are cprpared with the approximate alveolar oxygen partial pressures easily calculated by the physician’s bedside formula. As a result, we have concluded that the relative error of A-$aDe_2$ calculated by the bedside formula grows seriously for lower $F_{t}e_{2}$ values. The present prediction method of Alvitek is henceforth believed very meaningful to the physicians. The system hardware and software are described in the text.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.7
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• pp.1289-1295
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• 2007

In this paper, we implemented high-performance concurrent control system which manages whole RF systems with digital type and communicates with remote station on both wire and wireless networking. It consists of FPGA (Field Programmable Gate Array) part which controls forward/reverse LPA (Linear Power Amplifier), forward/reverse LNA (Low Noise Amplifier), channel cut wire/wireless TCP/IP, etc, master microprocessor (AVR), which manages the whole control system, Slave microprocessor which communicates SA (Spectrum Analyzer) and observes frequency spectrum of each channel with the resolution of 5KHz, 10 channel card microprocessor which independently observes each channel card and sets frequency synthesizer in channel cut and other peripherals and logics. The whole system is divided to two parts of H/W (hardware) and S/W (software) considering operational efficiency and concurrency, and implementation and cost. H/W consists of FPGA and microprocessor. We expected the optimized operation through H/W and SW co-design and hybrid H/W architecture.

• Journal of IKEEE
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• v.23 no.2
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• pp.388-394
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• 2019

This paper describes a design of security system-on-chip (SoC) that integrates a Cortex-M0 CPU with an AAW (ARIA-AES- Whirlpool) crypto-core which implements two block cipher algorithms of ARIA and AES and a hash function Whirlpool into an unified hardware architecture. The AAW crypto-core was implemented in a small area through hardware sharing based on algorithmic characteristics of ARIA, AES and Whirlpool, and it supports key sizes of 128-bit and 256-bit. The designed security SoC was implemented on FPGA device and verified by hardware-software co-operation. The AAW crypto-core occupied 5,911 slices, and the AHB_Slave including the AAW crypto-core was implemented with 6,366 slices. The maximum clock frequency of the AHB_Slave was estimated at 36 MHz, the estimated throughputs of the ARIA-128 and the AES-128 was 83 Mbps and 78 Mbps respectively, and the throughput of the Whirlpool hash function of 512-bit block was 156 Mbps.

• Journal of Advanced Navigation Technology
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• v.18 no.2
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• pp.191-199
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• 2014

Recently, researches to facilitate utilization by small and medium business (SMB) of cloud computing and big data paradigm, which is the booming adoption of IT area, has been on the increase. As one of these efforts, in this paper, we design and implement the prototype to tentatively build up Hadoop cluster under private cloud infrastructure environments. Prototype implementation are made on each hardware type such as single board, PC, and server and performance is measured. Also, we present the integrated verification results for the data analysis performance of the analysis software system running on top of realized prototypes by employing ASA (American Standard Association) Dataset. For this, we implement the analysis software system using several open sources such as R, Python, D3, and java and perform a test.