• Proceedings of the Korea Information Processing Society Conference
• /
• 2020.05a
• /
• pp.268-271
• /
• 2020

최근 동형암호에 대한 관심이 높아진 가운데, 이를 활용한 Cloud Computing 서비스를 구축하기 위한 시도가 이어지고 있다. 기존 동형암호 HW에 대한 연구는 수학적 기능 구현 자체에 중점을 두고 있다. 본 논문에서는 동형암호 CNN inference 모델 설계 과정에서 HW 구현 한계점과 bottleneck들을 수학적 기법이 아닌 HW 특징을 이용해서 극복하는 과정을 서술하였다.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.7
• /
• pp.159-166
• /
• 2013

This paper proposes an efficient loop accelerator for a motion estimation specific instruction-set processor. ME algorithms in nature contain complex and multiple loop operations. To support efficient hardware (HW) loop operations, this paper introduces four loop instructions and their specific HW architecture. The simulation results show that the proposed loop accelerator can reduce about 29% average instruction cycles for ME early-termination schemes compared with typical implementation having a combination of compare and conditional jump instructions. The proposed loop accelerator of the motion estimation specific instruction-set processor can significantly reduce the number of program memory accesses and greatly save power consumption. Hence, it can be quite suitable for low power and flexible ME implementation.

• Proceedings of the Plant Resources Society of Korea Conference
• /
• 2020.08a
• /
• pp.72-72
• /
• 2020

Various mixtures were prepared depending on the mixing ratio of Scutellaria baicalensis hot water extract (SB-HW) and Chrysanthemum morifolium ethanol extract (CM-E) and their anti-inflammatory activity were compared. Among them, SB-HW (80 ㎍/mL)/CM-E (120 ㎍/mL) or SB-HW (40 ㎍/mL)/CM-E (160 ㎍/mL) significantly inhibited LPS-stimulated NO and IL-6 levels in RAW 264.7 cells. The SB-HW (80 ㎍/mL)/CM-E (120 ㎍/mL) mixture, which was determined as active mixture, significantly reduced MUC5AC secretion in PMA and LPS-induced NCI-H292 cells. The active mixture also reduced the production of PGE2 and IL-8 in PMA-induced A549 cells. LC-MS/MS analysis showed that the active mixture was composed of high contents of flavone glycosides, such as baicalin and cynaroside. Western blot analysis indicated that the active mixture suppressed phosphorylation of ERK, JNK, and p38, associating with the inhibition of MAPK signaling. Taken together, our results suggest that the active mixture could be applied as a new anti-inflammatory herbal medicine

• The Korean Journal of Food And Nutrition
• /
• v.34 no.5
• /
• pp.477-486
• /
• 2021

To utilize Malus pruniforia Borkh. as a functional material, cold-water (CW), hot-water (HW), and 70% ethanol (EtOH) extracts were prepared, and their antioxidant and anti-inflammatory activities were compared. The antioxidant activity of the HW extract evaluated by ABTS and DPPH radical scavenging and FRAP activity was significantly effective. The total polyphenol content of the HW extract was also higher by 15.5±0.7 mg GAE/g extract compared to other extracts. The EtOH extract showed significantly decreased TNF-α (39.8%), IL-6 (65.5%), and NO (34.9%) levels in RAW 264.7 cells compared to the LPS-induced control group. The levels of IL-6 (21.1%) and IL-8 (19.3%) were significantly decreased by treatment of EtOH extract in HaCaT keratinocytes induced with TNF-α and IFN-γ. The UHPLC-MS results indicated that the EtOH extract might have chlorogenic acid and phlorizin as the major compounds. This was validated using HPLC-DAD, which showed that the EtOH extract had higher levels of chlorogenic acid and phlorizin (1,185±58 and 470±10 ㎍/g extract, respectively). In conclusion, the present study suggested that the anti-inflammatory activity of the EtOH extract was more effective than the CW and HW extracts, and chlorogenic acid and phlorizin could be used as indicator compounds and functional substances.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.8
• /
• pp.45-52
• /
• 2017

This paper presents a high-performance software-hardware dehazing system based on a dedicated hardware accelerator for the haze removal. In the proposed system, the dedicated hardware accelerator performs the dark-channel-prior-based dehazing process, and the software performs the other control processes. For this purpose, the dehazing process is realized as an OpenCL kernel by finding the inherent parallelism in the algorithm and is synthesized into a hardware by employing a high-level-synthesis technique. The proposed system executes the dehazing process much faster than the previous software-only dehazing system: the performance improvement is up to 96.3% in terms of the execution time.

• Journal of the Korea Society of Computer and Information
• /
• v.29 no.6
• /
• pp.1-12
• /
• 2024

Deep learning with faster and more accurate results requires large amounts of storage space and large computations. Accordingly, many studies are using hardware accelerators for quick and accurate calculations. However, the performance bottleneck is due to data movement between the hardware accelerators and the CPU. In this paper, we propose a data prefetch strategy that can efficiently reduce such operational bottlenecks. The core idea of the data prefetch strategy is to predict the data needed for the next task and upload it to local memory while the hardware accelerator (Matrix Multiplication Unit, MMU) performs a task. This strategy can be enhanced by using a dual buffer to perform read and write operations simultaneously. This reduces latency and execution time of data transfer. Through simulations, we demonstrate a 24% improvement in the performance of hardware accelerators by maximizing parallel processing with dual buffers and bottlenecks between memories with data prefetch.

• Journal of IKEEE
• /
• v.24 no.1
• /
• pp.186-193
• /
• 2020

In this paper, we propose a multi-threading system to support reconfigurable hardware accelerators on Zynq SoC. We implement high-performance JPEG decoder with reconfigurable 2D IDCT hardware accelerators to achieve maximum performance available on the platform. In this system, up to four reconfigurable hardware accelerators synchronized with SW threads can be dynamically reconfigured to provide adaptive computing capabilities according to the given image resolution and the compression ratio. JPEG decoding is operated using images with resolutions 480p, 720p, 1080p at the compression ratio of 7:1-109:1. We show that significant performance improvements are achieved as the image resolution or the compression ratio increase. For 1080p resolution, the performance improvement is up to 79.11 times with throughput speed of 99 fps at the compression ratio 17:1.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.44 no.5
• /
• pp.12-19
• /
• 2007

This paper presents an ASIP(Application Specific Instruction Set Processor) for implementation of H.264/AVC, called VSIP(Video Specific Instruction-set Processor). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has hardware accelerators for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. The proposed VSIP can efficiently perform in real-time video processing and it can support various profiles and standards.