• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.353-353
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• 2007

탄소나노튜브(CNT)의 tip 부분에 존재하는 금속 촉매 입자들은 불순물로써 나노전자소자에 응용하는데 좋지 않은 영향을 미칠 수 있다. 또한, 바이오센서에서 target 바이오 물질과 반응하는 물질을 CNT에 고정시키기 위해서는 CNT-tip을 개방시키는 것이 중요하다. 본 연구에서는 성장된 CNT의 tip부분에 존재하는 금속 촉매 입자의 제거와 CNT-tip을 개방하기 위해 $HNO_3$의 농도 (20, 40, 60)와 etching 시간 (5, 10, 15, 20, 25 min)에 따라 최적의 조건을 찾는 실험을 하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.152-153
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• 2006

본 연구에서는 태양전지 표면에 입사된 광자의 반사손실을 최소화하기 위한 방법으로써 기판 표면에 다공성 실리콘층을 이용한 반사방지막 (Anti-Reflection Coating, ARC)을 형성하는 실험을 하였다. 다공성 실리콘(Porous silicon, PSi)은 실온에서 일정 비율로 만든 전해질 용액($HF-C_2H_5OH-H_2O$)을 사용하여 실리콘 표면을 양극산화처리 함으로써 단순 공정만으로 실리콘 기판의 반사율을 높일 수 있다. 또한 새로운 레이어(layer)없이 기존 기판을 식각시켜 만들기 때문에 박막형 태양전지를 제작시 적용이 용이하다. 저비용, 단순공정의 이점을 살려 전류밀도에 따른 PSi의 반사방지막으로써의 특성을 비교 분석하였다.

• Korean Chemical Engineering Research
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• v.60 no.2
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• pp.313-319
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• 2022

AlGaN/GaN based HfO₂ MOSHEMT (metal oxide semiconductor high electron transistor) with different gate recess depth was simulate to demonstrate a successful normally-off operation of the transistor. Three types of the HEMT structures including a conventional HEMT, a gate-recessed HEMT with 3 nm thick AlGaN layer, and MIS-HEMT without AlGaN layer in the gate region. The conventional HEMT showed a normally-on characteristics with a drain current of 0.35 A at V_G = 0 V and V_DS = 15 V. The recessed HEMT with 3 nm AlGaN layer exhibited a decreased drain current of 0.15 A under the same bias condition due to the decrease of electron concentration in 2DEG (2-dimensional electron gas) channel. For the last HEMT structure, distinctive normally- off behavior of the transistor was observed, and the turn-on voltage was shifted to 0 V.

• Korean Chemical Engineering Research
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• v.44 no.5
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• pp.513-519
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• 2006

We developed two kinds of the microchip for application to electrophoresis based on both glass and quartz employing the MEMS fabrications. The poly-Si layer deposited onto the bonding interface apart from channel regions can play a role as the optical slit cutting off the stray light in order to concentrate the UV ray, from which it is possible to improve the signal-to-noise (S/N) ratio of the detection on a chip. In the glass chip, the deposited poly-Si layer had an important function of the etch mask and provided the bonding surface properly enabling the anodic bonding. The glass wafer including more impurities than quartz one results in the higher surface roughness of the channel wall, which affects subsequently on the microflow behavior of the sample solutions. In order to solve this problem, we prepared here the mixed etchant consisting HF and $NH_4F$ solutions, by which the surface roughness was reduced. Both the shape and the dimension of each channel were observed, and the electroosmotic flow velocities were measured as 0.5 mm/s for quartz and 0.36 mm/s for glass channel by implementing the microchip electrophoresis. Applying the optical slit with poly-Si layer provides that the S/N ratio of the peak is increased as ca. 2 times for quartz chip and ca. 3 times for glass chip. The maximum UV absorbance is also enhanced with ca. 1.6 and 1.7 times, respectively.

• Journal of the Korean Vacuum Society
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• v.13 no.1
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• pp.34-38
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• 2004

Hot embossing master is indispensable for the fabrication of polymeric optical waveguides using hot embossing technology. Sidewall roughness of silicon master is directly related to optical loss of optical waveguides In this paper, a silicon master was fabricated by using a deep-RIE process. Additionally, thermal oxidation followed by oxide removal was carried out to minimize etched Si sidewall roughness. Thermal oxidation and oxide removal were performed with $H_2O_2$ atmosphere at $1050^{\circ}C$ and $NH_4$F:HF=6:l BOE, respectively, for the oxide thickness of 400$\AA$, 1000$\AA$, 3000$\AA$, 4500$\AA$, 5600$\AA$ and 6200$\AA$. The sidewall roughness was characterized by SEM and SPM-AFH measurements. We found that the roughness was improved from 12nm (RMS) to 6nm (RMS) for the scalloped sidewall and from 162nm (RMS) to 39nm (RMS) for the vertical striation sidewall, respectively.

• Journal of the Korean Ceramic Society
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• v.41 no.7
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• pp.528-533
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• 2004

Macroporous SiC with pore size 84∼658 nm and mesoporous SiC with pore size 15∼65 nm were respectively prepared by infiltrating low viscosity preceramic polymer solutions into the various sacrificial templates obtained by natural sedimentation or centrifuge of 20∼700 nm silica sol, which were subsequently etched off with HF after pyrolysis at 1000∼140$0^{\circ}C$ in an argon atmosphere. Three-dimensionally long range ordered macroporous SiC ceramics derived from polymethylsilane (PMS) showed surface area 584.64$m^2$g$^{-1}$ when prepared with 112nm silica sol and at 140$0^{\circ}C$, whereas mesoporous SiC from polycarbosilane (PCS) exhibited the highest surface area 619.4 $m^2$g$^{-1}$ with random pore array when prepared with 20-30 nm silica sol and at 100$0^{\circ}C$. Finally, tile pore characteristics of porous SiC on the types of silica sol, polymers and pyrolytic conditions were interpreted with the analytical results of SEM, TEM, and BET instruments.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.20 no.1
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• pp.7-11
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• 2010

The reduction of optical losses in mono-crystalline silicon solar cell by surface texturing is a critical step to improve the overall cell efficiency. In this study, we have changed the sub-micrometer structure on the micrometer pyramidal structure by 2-step texturing. The Ag particles were coated on the micrometer pyramid surface in $AgNO_3$ solution, and then the etching with hydrogen fluoride and hydrogen peroxide created even smaller nano-pyramids in these pyramids. As a result, we observed that the changes of size and thickness of nano structure on pyramidal surface were determined by $AgNO_3$ concentration and etching time. Using 2-step texturing, the surface of wafers is etched to resemble the rough surface of a lotus leaf. Lotus surface can reduce average reflectance from 10% to below 3%. This reflectance is less than conventional textured wafer including anti-reflection coating.

• Journal of Surface Science and Engineering
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• v.41 no.5
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• pp.189-193
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• 2008

In this study, we carried out an investigation of the etching characteristics (etch rate, selectivity to $SiO_2$ and $HfO_2$) of TiN thin films in the $CH_4$/Ar inductively coupled plasma. The maximum etch rate of $274\;{\AA}/min$ for TiN thin films was obtained at $CH_4$(80%)/Ar(20%) gas mixing ratio. At the same time, the etch rate was measured as function of the etching parameters such as RF power, Bias power, and process pressure. The X-ray photoelectron spectroscopy analysis showed an efficient destruction of the oxide bonds by the ion bombardment as well as showed an accumulation of low volatile reaction products on the etched surface. Based on these data, the ion-assisted chemical reaction was proposed as the main etch mechanism for the $CH_4$ containing plasmas.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.833-836
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• 2005

Nano-gap trench is fabricated by the novel electrochemical etching technique using forward biased PN junction formed at the backside of the wafer. PN junction is formed using boron nitride wafer and the concentration of the boron doping is the high value of $1{\times}10^{19}$ $cm^{-3}$. The electro-chemical etching is performed in the 5% HF solution under the forward bias voltage of $1{\sim}2V$. The relationship between the etch rate of the trench and the voltage of the forward bias is investigated and the dependence of the gap for the voltage also examined. The etch rate increase from 0.027 ${\mu}m/min$ to 0.031 ${\mu}m/min$ as the value of the applied voltage increase from 1V to 2V, but the the gap is kept constant value of 40 nm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.19-20
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• 2006

Two methods that can reduce reflectance in solar cells are surface texturing and anti-reflection coating. Wet chemical etching is a typical method that surface texturing of multi-crystalline silicon. Wet chemical etching methods are the acid texturization of saw damage on the surface of multi-crystalline silicon or double-step chemical etching after KOH saw damage removal too. These methods of surface texturing are realized by chemical etching in acid solutions HF-$HNO_3$-$H_2O$. In this solutions we can reduce reflectance spectra by simple process etching of multi-crystalline silicon surface. We have obtained reflectance of 27.19% m 400~1100nm from acidic chemical etching after KOH saw damage removal. This result is about 7% less than just saw damage removal substrate. The surface morphology observed by microscope and scanning electron microscopy (SEM).