• Journal of Broadcast Engineering
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• v.15 no.4
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• pp.498-512
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• 2010

Intra coding is an indispensable coding tool since it can provide random accessibility as well as error resiliency. However, it is the problem that intra coding has relatively low coding efficiency compared with inter coding in the area of video coding. Even though H.264/AVC has significantly improved the intra coding performance compared with previous video standards, H.264/AVC encoder complexity is significantly increased, which is not suitable for low bit rate interactive services. In this paper, a Voting-based Intra Mode Bit Skip (V-IMBS) scheme is proposed to improve coding efficiency as well as to reduce encoding time complexity using decoder-side prediction. In case that the decoder can determine the same prediction mode as what is chosen by the encoder, the encoder does not send that intra prediction mode; otherwise, the conventional H.264/AVC intra coding is performed. Simulation results reveal a performance increase up to 4.44% overall rate savings and 0.24 dB in peak signal-to-noise ratio while the frame encoding speed of proposed method is about 42.8% better than that of H.264/AVC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.45-53
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) encoding. Previous CAVLC architectures search all of the coefficients to find statistic characteristics in a block. However, it is unnecessary information that zero coefficients following the last position of a non-zero coefficient when CAVLC encodes residual coefficients. In order to reduce this unnecessary operation, we propose two techniques, which detect the first and last position of non-zero coefficients and arrange non-zero coefficients sequentially. By adopting these two techniques, the required processing time was reduced about 23% compared with previous architecture. It was designed in a hardware description language and total logic gate count is 16.3k using 0.18um standard cell library Simulation results show that our design is capable of real-time processing for $1920{\times}1088\;30fps$ videos at 81MHz.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.11a
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• pp.110-112
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• 2011

GPU의 병렬성과 연산능력을 일반적인 공학적 문제 해결에 적용하는 GPGPU 컴퓨팅에 대한 연구가 최근 활발히 진행되고 있다. 비디오 압축과정에는 많은 양의 화소 데이터에 동일하게 반복되는 연산을 수행하는 알고리즘이 많이 적용되므로 GPGPU를 통한 고속 병렬 계산의 응용 분야로 매우 적합하다. H.264/AVC는 비디오를 압축하는 가장 최신의 국제표준으로 여러 제품군과 서비스에 대한 적용되어 시장에서 널리 사용되고 있다. 본 논문에서는 GPGPU의 응용 분야로 주목 받고 있는 비디오 압축 분야에 대한 적용으로 H.264/AVC의 화면내 예측 모드 결정과정에 GPGPU 병렬 프로그래밍을 적용하여 예측 모드 결정 속도를 향상하는 방법을 제안한다. GPU상에서의 데이터 병렬처리를 위해 CUDA C언어를 사용하였으며, CPU상에서의 연산은 C언어를 사용하여 구현되었다. GPU상에서 프레임 전체에 대한 화면내 예측 모드를 병렬적으로 결정함으로써 이에 소요되는 시간을 줄여 줄 수 있었다. 실험결과 GPU상에서 병렬적으로 예측 모드를 결정할 때 Full-HD급 영상에서 약 2.8배 정도의 속도 향상을 확인할 수 있었다. 향후 GPGPU 병렬 프로그래밍을 화면 내 예측뿐만 아니라 반복되는 연산을 수행하는 다른 알고리즘에도 적용하여 부호화기의 계산 부담을 덜어준다면 고속 실시간 비디오 압축 부호기 개발이 더욱 용이해 질것으로 기대된다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.431-435
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• 2011

This paper presents optimized searching technique to improve the performance of H.264/AVC. The proposed CAVLC encoder uses forward and backward searching algorithm to compute the parameters. By zero-block skipping technique and pipelined scheduling, the proposed CAVLC encoder can obtain better performance. The experimental result shows that the proposed architecture needs only 66.6 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 13.8% than that of previous designs. The proposed CAVLC encoder was implemented using VerilogHDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 15.6K with 125Mhz clock frequency.

• Journal of Broadcast Engineering
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• v.16 no.3
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• pp.448-461
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• 2011

H.264/AVC significantly outperforms the previous video coding standards with many new coding tools. Among these tools, several intra-block coding tools can particularly improve coding efficiency. For intra prediction, H.264/AVC supports most probable mode in the entropy coding process to reduce syntax elements indicating intra prediction modes and most probable mode selection ratio is very high. Also, in general, natural images and videos have many homogeneous regions whose high correlation with neighbouring blocks. In this paper, we propose intra prediction mode SKIP mode using decoder-side prediction to improve the coding efficiency. The proposed method is determined the optimal prediction mode using only neighbouring block's information and coded on the basis of the conventional prediction/transform coding. And the prediction modes are not send to decoder at all. Skipped intra prediction mode is determined by decoder. Experimental results show that the proposed method achieves coding gains of 1.40% for common intermediate format(CIF), 3.24% for 720p sequences against the H.264/AVC JM 17.0 reference software.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.11a
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• pp.184-185
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• 2012

H.264/AVC 는 다중 참조영상을 사용하여 움직임 예측/보상을 수행함으로써 보다 높은 부호화 효율을 얻을 수 있지만 다중 참조영상에 대한 움직임 예측으로 인하여 부호화 복잡도 증가를 야기한다. 본 논문에서는 공간적 상관성을 이용하여 참조영상 수를 제한함으로써 부호화기의 복잡도를 줄이는 고속 참조영상 결정 기법을 제안한다. 즉, 주변 블록의 부호화 정보와 현재 부호화하는 매크로블록의 $16{\times}16$ 화면간 예측 결과를 적응적으로 이용하여 참조영상 후보의 수를 줄인다. 모의실험에서 제안한 알고리즘은 JM17.2 에 비해 0.67%의 평균 비트율 증가의 미미한 부호화 효율 감소에 평균 47% 정도의 부호화 시간을 감소하였으며, 기존의 고속 기법보다 우수한 성능을 보임을 확인하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.805-807
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• 2005

H.264/AVC의 프레임내 예측기법은 현 매크로블록의 이웃픽셀들로부터 예측값을 추출함으로써 인트라 픽처의 압축률을 높이는데 크게 기여했다. 그러나 모든 매크로블록에 대해 총 17가지의 후보 모드를 검사해야 하기 때문에, 전체 부호화기의 복잡도를 상당히 상승시키는 요인이기도 하다. 본 논문에서는 이 문제를 해결하기 위해, 기존의 움직임 추정 전용 하드웨어로 주로 사용되는 1차원 시스톨릭 어레이 구조에 부가적인 하드웨어를 장착하여, 움직임 추정뿐만 아니라 프레임 내 예측까지 가능한 하드웨어 구조를 제안한다. 병렬적으로 끊김이 없는 수행을 위해 프레임내 예측 알고리즘을 약간 수정했으나, 이것은 화질이나 비트스트림 크기에 영향을 거의 미치지 않는다. 제안된 구조는 연산에 대한 명령어 개수로 비교할 때, ARM 기반 시스템에서 얻을 수 있는 성능의 10배에서 40배에 달하는 높은 성능을 보여준다.

• Journal of Broadcast Engineering
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• v.20 no.1
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• pp.171-182
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• 2015

HEVC can increase the coding efficiency significantly compared with H.264/AVC however it requires much larger computational complexities in both encoder and decoder. In this paper, the decision process of inter-prediction modes in the HEVC reference software has been studied and a fast algorithm to reduce the computational complexity of encoder and decoder is introduced. The proposed scheme introduces a early decision criteria using the outputs of uni-directional predictions to skip the bi-directional prediction estimation. From the experimental results, it was proven that the proposed method can reduce the encoding complexity by 12.0%, 14.6% and 17.2% with 0.6%, 1.0% and 1.5% of coding efficiency penalty, respectively. In addition, the ratio of bi-directional prediction mode was reduced by 6.3%, 11.8% and 16.6% at the same level of coding efficiency penalty, respectively, which should lead to the decoder complexity reduction. Finally, the effects of the proposed scheme are maintained regardless of the use of the early skip decision algorithm which is implemented in the HEVC reference software.

• Journal of Korea Multimedia Society
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• v.14 no.7
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• pp.849-857
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• 2011

Gaming on demand(GOD) makes people enjoy games by encoding and transmitting game screen at a server side, and decoding the video at a client side. In this paper, we propose a fast game video encoder for multiple users over network with low-powered devices. In the proposed system, the computational complexity of game encoders is reduced by using scene descriptors, which consists of an object motion vector, global motion, and scene change. With additional information from game engines, the proposed encoder does not need to perform various complexity processes such as motion estimation and ratedistortion optimization. The motion estimation and rate-distortion optimization skipped by scene descriptors. We found that the proposed method improved 192 % in terms of FPS, compared with x264 software. With partial assembly code, we also improved coding speed by 86 % in terms of FPS. We found that the proposed fast encoder could encode over 60 FPS for real-time GOD applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3C
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• pp.102-111
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• 2005

In this paper, we propose an advanced hardware architecture for the fast inter prediction engine of the video coding standard MPEG-4 AVC. We describe the algorithm and derive the hardware architecture emphasizing and real time operation of the quarter_pel based motion estimation. The fast inter prediction engine is composed of block segmentation, motion estimation, motion compensation, and the fast quarter_pel calculator. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur & Virtex2 FPGA, and also by synthesis on Samsung 0.18 um CMOS technology. The synthesis result shows that the proposed hardware can operate at 62.5MHz. In this case, it can process about 88 QCIF video frames per second. The hardware is being used as a core module when implementing a complete MPEG-4 AVC video encoder chip for real-time multimedia application.