• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.651-654
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• 2005

In this paper, an efficient switching pattern to equalize the size of transformer is proposed for a multi-level inverter employing cascaded transformers. It is based on the prior selected harmonic elimination PWM(SHEPWM) method. Because the maximum magnetic flux imposed on each transformer becomes exactly equal each to each, all transformers can be designed with the same size regardless of their position. Therefore, identical full-bridge inverter units can be utilized, thus improving modularity and manufacturability. The fundamental idea of the proposed switching pattern is illustrated and the analyzed theoretically. The validity of the proposed switching strategy is verified by experimental results.

• Transactions on Electrical and Electronic Materials
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• v.18 no.4
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• pp.229-236
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• 2017

This paper deals with the design and implementation of an efficient topology for cascaded multilevel inverters with reduced part counts. In the proposed design, a well-established basic unit is first developed. The series extension of this unit results in the formation of the proposed multilevel inverter. The proposed design minimizes the number of power electronic components including insulated-gate bipolar transistors and gate driver circuits, which in turn cuts down the size of the inverter assembly and reduces the operating power losses. An explicit control strategy with enhanced device efficiency is also acquired. Thus, the part count reductions enhance not only the economical merits but also the technical features of the entire system. In order to accomplish the desired operational aspects, three algorithms are considered to determine the magnitudes of the dc voltage sources effectively. The proposed topology is compared with the conventional cascaded H-bridge multilevel inverter topology, to reflect the merits of the presented structure. In continue, both the analytical and experimental results of a cascaded 31-level structure are analyzed. The obtained results are discussed in depth, and the exemplary performance of the proposed structure is corroborated.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.433-434
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• 2017

기존의 전력 시스템에서 큰 부피를 차지하는 계통 주파수(50/60Hz) 변압기를 대체하기 위해서, 최근 전력용 반도체 변압기 SST(Solid State Transformer)에 대한 연구가 많이 수행되고 있다. AC/DC 컨버터는 높은 시스템 입력 전압에 대응 가능한 기존의 다양한 멀티레벨 컨버터 중 CHB (Cascaded H-bridge) 컨버터는 시스템 모듈화의 용이성과 상용 소자의 정격전압을 고려했을 때 반도체 변압기 시스템에 가장 많이 적용되고 있는 토폴로지이지만 각각의 H-bridge 컨버터 DC-link 전압의 불평형 문제가 발생한다. 본 논문에서는 CHB 컨버터의 전압 불평형을 해결하기 위하여 추가적인 센서가 필요없는 간단하고 실용적인 전압 불평형 보상 제어기를 제안한다.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.5
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• pp.424-431
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• 2007

This thesis proposed H-Bridge Multi-Level Inverter for Fluidized Bed Combustion Boiler Secondary Air Fan in 200MW thermal power plant. The adjustable speed drive systems improve the efficiency in lightly load condition and extend the life span of motor by limiting the over current at starting. H-Bridge Multi-level Inverter is composed of the several series low voltage power cell inverters, which have the independent isolated do link, in each phase. KEPRI(Korea Electric Power Research Institute) has successfully completed to develop, install, and commission H-Bridge Multi-level Inverter(6.6kV, 1MVA). This thesis gives a full detail about H-Bridge Multi-level Inverter, proposed boiler DCS(Distributed Control System) logic, and commissioning test result.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.320-321
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• 2011

This paper proposes a practical design and development for CHBM inverter based on Power Electronics Building Blocks (PEBB). It is shown that the expansion and modularization characteristics of the CHBM inverter are improved since the individual inverter modules operate more independently, when using the PEBB concept. The proposed design and control methods are described in detail and the validity of the proposed system is verified experimentally in various industrial fields.

• Journal of Electrical Engineering and Technology
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• v.13 no.4
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• pp.1528-1538
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• 2018

In this paper, configuration of $1-{\phi}$ seven-level boost DC-link cascade based reversing voltage multilevel inverter (BDCLCRV MLI) is proposed for uninterrupted power supply (UPS) applications. It consists of three level boost converter, level generation unit and full bridge circuit for polarity generation. When compared with conventional boost cascaded H-bridge MLI configurations, the proposed system results in reduction of DC sources, reduced power switches and gate drive requirements. Inverter switching is accomplished by providing appropriate switching angles that is generated by any optimization switching angle techniques. Here, round modulation control (RMC) method is taken as the optimization method and switching angles are derived and the same is compared with various switching angles methods i.e., equal-phase (EP) method, and half-equal-phase (HEP) method which results in improved quality of obtained AC power with lowest total harmonic distortion (THD). Reduction in DC sources and switch count makes the system more cost effective. A simulation and prototype model of $1-{\phi}$ seven-level BDCLCRV MLI system is developed and its performance is analyzed for various operating conditions.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.536-537
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• 2013

전기로와 같은 고압, 대용량의 산업응용분야에서 전원 안정화를 목적으로 하는 변동부하에 의해 발생되는 정상분 및 역상분의 무효전력을 보상하기 위한 고성능의 STATCOM의 개발이 요구되었다. 본 논문에서는 POSCO ICT에서 개발한 22.9kV 5MVA STATCOM(static synchronous compensator)에 대해 기술하였다. 개발된 STATCOM은 다단 멀티레벨 컨버터(Cascaded Multilevel Converter) 방식으로 Delta 구성하였으며, 각상당 12개의 H-Bridge Inverter가 직렬로 구성되어 25 레벨의 전압을 출력한다.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.4
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• pp.332-341
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• 2014

A cascaded H-bridge multi-level STATCOM(STATic synchronous COMpensator), which is composed of many cell inverters with independent dc-sources, generates inevitably dc-side voltage unbalance among phases when it compensates unbalanced load. It comes from the difference of flowing active power in each phase when this compensator makes negative-sequence current to eliminate the unbalance of source-side current. However, this unbalance can be controlled by injecting zero-sequence current which is decoupled with grid currents, so the compensator can work well during this balancing process. Both a feedback control algorithm, which produces zero-sequence current proportional to dc-side voltage unbalance within each phase, and a feedforward control algorithm, which makes zero-sequence current directly from the compensator's negative-sequence current, were proposed. The dc-side voltage of each phase can be controlled stably by these proposed algorithms in both steady-state and transient, so the compensator can have fast response to satisfy control performance under rapid changing load. These balancing controllers were implemented and verified via simulation and experiment.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.974-975
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• 2006

본 논문에서는 대용량 전력 변환 장치이며 출력 전압 가변이 가능한 H-브릿지 멀티레벨 인버터의 제어 알고리즘을 제안한다. H-브릿지 멀티레벨 인버터는 독립적으로 절연된 직류 부를 갖는 저압의 단상 인버터(셀 유닛)를 다수 직렬 접속하여 고압 3상 전압을 출력하는 Cascaded H-bridge 전압형 인버터이다. 다수의 독립 절연 직류부를 만들기 위해 입력 측에 다권선 변압기를 사용하여 입력 측 고조파 함유율을 축소시킬 수 있다. 인버터를 사용하는 제어방법 중 가장 오래되고 일반적인 방법으로 출력전압과 출력 주파수의 비를 일정하게 제어하여 전동기의 자속 크기를 일정하게 제어하고, 별도의 센서 없이도 운전이 가능한 V/F 제어모드는 저속 모드에서 제어 성능이 떨어지는 것을 실험을 통해 확인할 수 있었다. 정격용량 180kVA이고 출력 전압 480V인 H-브릿지 멀티 레벨 인버터 실험을 통해 벡터제어와 센서리스 벡터제어를 구현하여 저속 모드에서 제어 성능의 향상을 입증하였다.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1706-1715
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• 2016

In this paper, a single phase modified switched-diode topology for both symmetrical and asymmetrical cascaded multilevel inverters is presented. It consists of a Modified Switched-Diode Unit (MSDU) and a Twin Source Two Switch Unit (TSTSU) to produce distinct positive voltage levels according to the operating modes. An additional H-bridge synthesizes a voltage waveform, where the voltage levels of either polarity have less Total Harmonic Distortion (THD). Higher-level inverters can be built by cascading MSDUs. A comparative analysis is done with other topologies. The proposed topology results in reductions in the number of power switches, losses, installation area, voltage stress and converter cost. The Nearest Level Control (NLC) technique is employed to generate the gating signals for the power switches. To verify the performance of the proposed structure, simulation results are carried out by a PSIM under both steady state and dynamic conditions. Experimental results are presented to validate the simulation results.