• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.2
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• pp.74-79
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• 2003

The method of the analysis of the base Gummel number of the BJT(Bipolar Junction Transistor) for integrated circuits based upon the semiconductor physics is proposed and the method of calculating the doping profile of the base region using process conditions is presented. The transistor saturation current obtained from the proposed method of NPN BJT using 20V and 30V process shows an averaged relative error of 6.7% compared with the measured data and the transistor saturation current of PNP BJT shows an averaged relative error of 9.2% compared with the measured data

• Proceedings of the KIEE Conference
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• 2002.11a
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• pp.141-144
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• 2002

The method of the analysis of the base Gummel number of the PNP BJT(Bipolar Junction Transistor) for integrated circuits based upon the semiconductor physics is proposed and the method of calculating the doping profile of the base region using process conditions is presented. The transistor saturation current obtained from the proposed method of PNP BJT using 20V and 30V process shows an averaged relative error of 6.7% compared with the measured data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.13-20
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• 2003

The model of the transistor saturation current of the BJT for integrated circuits based upon the semiconductor physics is proposed. The method for calculating the doping profile in the base region using process conditions is presented and the method for calculating the base Gummel number of lateral PNP BJT and vertical NPN BJT is proposed. The transistor saturation currents of NPN BJT using 20V and 30V process conditions obtained from the proposed method show an average relative error of 6.7% compared with the measured data and the transistor saturation currents of PNP BJT show an average relative error of 6.0% compared with the measured data.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.8
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• pp.41-51
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• 1997

The device simulator (BANDIS) which can analyze efficiently the electrical characteristics of the semiconductor devices under the three dimensional stationary conditions on the IBM PC was developed. Poisson, electon and hole continuity equations are discretized y te galerkin method using a tetrahedron as af finite element. The frontal solver which has exquisite data structures and advanced input/output functions is dused for the matrix solver which needs the highest cost in the three dimensional device simulation. The discretization method of the continuity equations used in BANDIS are compared with that of the scharfetter-gummel method used in the commercial three-dimensional device. To verify an accuracy and the efficiency of the discretization method, the simulation results of the PN junction diode and the BJT from BANDIS are compared with those of the commercial three-dimensiional device simulator such as DAVINCI. The maximum relative error within 2% and the average number of iterations needed for the convergence is decreased by more than 20%. The total simulation time of the BJT with 25542 nodes is decreased to about 60% compared with that of DAVINCI.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.221-221
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• 2014

The present work proposes an improved numerical simulator for design and modification of large area capacitively coupled plasma (CCP) processing chamber. CCP, as notoriously well-known, demands the tremendously huge computational cost for carrying out transient analyses in realistic multi-dimensional models, because electron dissociations take place in a much smaller time scale (${\Delta}t{\approx}10-8{\sim}10-10$) than time scale of those happened between neutrals (${\Delta}t{\approx}10-1{\sim}10-3$), due to the rf drive frequencies of external electric field. And also, for spatial discretization of electron flux (Je), exponential scheme such as Scharfetter-Gummel method needs to be used in order to alleviate the numerical stiffness and resolve exponential change of spatial distribution of electron temperature (Te) and electron number density (Ne) in the vicinity of electrodes. Due to such computational intractability, it is prohibited to simulate CCP deposition in a three-dimension within acceptable calculation runtimes (<24 h). Under the situation where process conditions require thickness non-uniformity below 5%, however, detailed flow features of reactive gases induced from three-dimensional geometric effects such as gas distribution through the perforated plates (showerhead) should be considered. Without considering plasma chemistry, we therefore simulated flow, temperature and species fields in three-dimensional geometry first, and then, based on that data, boundary conditions of two-dimensional plasma discharge model are set. In the particular case of SiH4-NH3-N2-He CCP discharge to produce deposition of SiNxHy thin film, a cylindrical showerhead electrode reactor was studied by numerical modeling of mass, momentum and energy transports for charged particles in an axi-symmetric geometry. By solving transport equations of electron and radicals simultaneously, we observed that the way how source gases are consumed in the non-isothermal flow field and such consequences on active species production were outlined as playing the leading parts in the processes. As an example of application of the model for the prediction of the deposited thickness uniformity in a 300 mm wafer plasma processing chamber, the results were compared with the experimentally measured deposition profiles along the radius of the wafer varying inter-electrode gap. The simulation results were in good agreement with experimental data.