• 전기학회논문지
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• 제62권2호
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• pp.201-207
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• 2013

This paper propose seamless transfer operation between grid-connected and stand-alone mode in the three-phase inverter for microgrid. The inverter operates grid-connected mode and stand-alone mode. Grid-connected mode is the inverter connected to grid and stand-alone mode is to deliver energy to the load from inverter at grid fault. When conversion from gird-connected to stand-alone mode, the inverter changes current control to voltage control. When grid restored, the inverter system is conversion from stand-alone to grid-connected mode. In this case, load phase and grid phase are different. Therefore, synchronization is essential. Thus Seamless transfer operation stand-alone to grid-connected mode. In this paper, propose sealmless transfer operation between grid-connceted and stand-alome mode, and this method is verified through simulation and experiment.

• 전기학회논문지
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• 제56권3호
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• pp.547-555
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• 2007

In order to transmit energy generated through the stator winding of a doubly-fed induction generator (DFIG), we need to synchronize the generated voltage vector with the grid voltage vector. However, the existing synchronization methods work only when the encoder is installed at a specific position and equivalent constant is precise. In order to solve this problem, a new synchronization method has been proposed and a way of applying the method to existing doubly-fed induction generator control algorithm has been also proposed. The validities of the methods proposed were verified by using a prototype converter for a 1.5MW-class doubly-fed induction generator and experimental results showed the validity of that against variation of an encoder positions, generator parameters, and grid voltages.

• 전력전자학회논문지
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• 제20권1호
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• pp.72-80
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• 2015

In distributed generation systems, a grid-connected inverter should operate with synchronization to grid voltage. Considering that synchronization requires the phase angle of grid voltage, a phase locked loop (PLL) scheme is often used. The synchronous reference frame phase locked loop (SRF-PLL) is generally known to provide reasonable performance under ideal grid voltage. However, this scheme indicates performance degradation under the harmonic distorted or unbalanced grid voltage condition. To overcome this limitation, this paper proposes a phase and harmonic detection method of grid voltage using fast Fourier transform (FFT). To reduce the calculation time of FFT algorithm, minimum sampling data is taken from the voltage measurement to determine the phase angle and the magnitude of harmonic components. An experimental test setup for a grid-connected inverter system has been constructed. By comparative simulations and experiments under various abnormal grid voltage conditions, the proposed scheme has been proven to effectively track the phase angle of the grid voltage.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 추계학술대회
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• pp.104-106
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• 2018

The harmonics and the DC offset in the grid can cause serious synchronization problems for grid connected inverters (GCIs) which leads not able to satisfy the IEEE 519 and p1547 standards in terms of phase and frequency variations. In order to guarantee the smooth and reliable synchronization of GCIs with the grid, Phase Locked Loop (PLL) is the crucial element. Typically, the performance of the PLL is assessed to limit the grid disturbances e.g. grid harmonics, DC Offset and voltage sag etc. To ensure the quality of GCI, the PLL should be precise in estimating the grid amplitude, frequency and phase. Therefore, in this paper a novel Robust PLL technique called Digital Lock-in Amplifier (DLA) PLL is proposed. The proposed PLL estimate the frequency variations and phase errors accurately even in the highly distorted grid voltage conditions like grid voltage harmonics, DC offsets and grid voltage sag. To verify the performance of proposed method, it is compared with other six conventional used PLLs (CCF PLL, SOGI PLL, SOGI LPF PLL, APF PLL, dqDSC PLL, MAF PLL). The comparison is done by simulations on MATLAB Simulink. Finally, the experimental results are verified with Single Phase GCI Prototype.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2013년도 전력전자학술대회 논문집
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• pp.47-48
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• 2013

In order to evaluate the response of the grid-connected systems, Phase lock technology is widely used in power electronic devices to obtain the phase angle, amplitude, and frequency of the grid voltage because phase locked loop (PLL) algorithms are very important for grid synchronization and monitoring in the grid connected power electronic devices. This paper presents a performance evaluation in tracking grid angular frequency through single phase synchronization techniques which are an enhanced PLL (EPLL), second-order generalized integrator-PLL (SOGI-PLL), and second-order generalized integrator-frequency locked loop (SOGI-FLL). These techniques are properly analyzed through several steps to get the best technique which can track the frequency accurately and smoothly.

• 전력전자학회논문지
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• 제23권6호
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• pp.381-388
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• 2018

A novel and simple algorithm for accurate calculation of RMS voltage is proposed in a digitally controlled grid-tie inverter system. Given that the actual frequency of grid voltage is continuously changing, the constant sampling frequency cannot be a multiple number of the fundamental frequency. Therefore, the RMS of grid voltage contains periodic oscillations due to the differences in the phase angle of sampled data during calculation. The proposed algorithm precisely calculates and updates the initial phase angle of the first sampled voltage in a half-cycle period using phase-locked loop, which is commonly utilized for phase angle detection in grid-tie inverter systems. The accuracy and dynamic performance of the proposed algorithm are compared with those of other algorithms through various simulations and experiments.

• 전력전자학회논문지
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• 제13권6호
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• pp.447-452
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• 2008

본 논문은 단상 그리드전압의 동기화에 가장 적합한 곱형 PLL 시스템을 설계한다. 소신호 해석방법으로 PLL 시스템을 모델링하고, 동기 과도 응답특성뿐만 아니라 동기신호의 왜곡을 고려하여 저역필터의 차단주파수 및 이득의 최적 값을 유도한다. 설계의 성능을 검증하기 위하여, 시뮬레이션 및 실험결과로 차단주파수 및 이득의 변화에 동기신호의 과도응답과 리플성분을 관찰한다.

• 전력전자학회논문지
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• 제23권4호
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• pp.231-239
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• 2018

The phase-locked loop (PLL) is widely used in grid-tie inverter applications to achieve a synchronization between the inverter and the grid. However, its performance deteriorates when the grid voltage is not purely sinusoidal due to the harmonics and the frequency deviation. Therefore, a high-performance PLL must be designed for single-phase inverter applications to guarantee the quality of the inverter output. This paper proposes a simple method that can improve the performance of the PLL for the single-phase inverter under a non-sinusoidal grid voltage condition. The proposed PLL can accurately estimate the fundamental frequency and theta component of the grid voltage even in the presence of harmonic components. In addition, its transient response is fast enough to track a grid voltage within two cycles of the fundamental frequency. The effectiveness of the proposed PLL is confirmed through the PSIM simulation and experiments.

• Journal of Power Electronics
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• 제18권5호
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2017년도 추계학술대회
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• pp.7-8
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• 2017

The Phase-Locked Loop (PLL) is widely used in grid-tie inverter applications to achieve the synchronization between the inverter and the grid. However, its performance is deteriorated when the grid voltage is not pure sinusoidal due to the harmonics and the frequency deviation. Therefore it is important to design a high performance phase-locked loop (PLL) for the single phase inverter applications to guarantee the quality of the inverter output. In this paper a simple method to improve the performance of the PLL for the single phase inverter is proposed. The proposed PLL is able to accurately estimate the fundamental frequency component of the grid voltage even in the presence of harmonic components. In additional its transient response is fast enough to track a change in grid voltage within two cycles of the fundamental frequency. The effectiveness of the proposed PLL is confirmed through the PSIM simulation and experiments.