• Title/Summary/Keyword: Graphic processor

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DEVELOPMENT OF PRE/POST PROCESSOR PROGRAM FOR NUFLEX (NUFLEX의 전후처리장치 개발)

  • Kim, Sa-Ryang;Yeo, Jae-Hyun;Won, Chan-Shik;Hur, Nahm-Keon
    • 한국전산유체공학회:학술대회논문집
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    • 2007.04a
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    • pp.91-94
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    • 2007
  • A GUI based pre/post processor program, which is based on the MFC and OpenGL library in the Windows O/S, hee been developed for NUFLEX Using this program, users are able to generate and modify structured or unstructured grid geometries, set all the parameters for the solver, and observe the results of the simulation in graphic view by vector or scalar plots. The mesh geometry data can be imported from or exported to other programs by supporting functions for reading from and writing to CGNS data format files.

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Pre-processor for Building Structural Analysis by CAD system (CAD를 이용한 건축구조해석용 Pre-processor 구축)

  • 고일두;송석환
    • Proceedings of the Computational Structural Engineering Institute Conference
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    • 1992.10a
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    • pp.112-120
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    • 1992
  • The use of Pre-processor for building structural analysis used to rely upon filling up fixed format data, which was ineffective and error-prone. This research attempts to integrate structural analysis system with DBMS and CAD system in order to make it easy to exchange data between pre-process, analysis, and post-process stages. Automatic generation of database from pre-process stage allows easy preparation of main input data for other structural analysis programs. CAD system with some sub-programs written in LISP and C works as a graphic user interface. This approach gives an easy, effective and error-free way of inputing data for structural analysis.

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A design of Floating Point Arithmetic Unit for Geometry Operation of Mobile 3D Graphic Processor (모바일 3D 그래픽 프로세서의 지오메트리 연산을 위한 부동 소수점 연산기 구현)

  • Lee, Jee-Myong;Lee, Chan-Ho
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.711-714
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    • 2005
  • We propose floating point arithmetic units for geometry operation of mobile 3D graphic processor. The proposed arithmetic units conform to the single precision format of IEEE standard 754-1985 that is a standard of floating point arithmetic. The rounding algorithm applies the nearest toward zero form. The proposed adder/subtraction unit and multiplier have one clock cycle latency, and the inversion unit has three clock cycle latency. We estimate the required numbers of arithmetic operation for Viewing transformation. The first stage of geometry operation is composed with translation, rotation and scaling operation. The translation operation requires three addition and the rotation operation needs three addition and six multiplication. The scaling operation requires three multiplication. The viewing transformation is performed in 15 clock cycles. If the adder and the multiplier have their own in/out ports, the viewing transformation can be done in 9 clock cycles. The error margin of proposed arithmetic units is smaller than $10^{-5}$ that is the request in the OpenGL standard. The proposed arithmetic units carry out operations in 100MHz clock frequency.

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An Implementation of 3D Graphic Accelerator for Phong Shading (퐁 음영법을 위한 3차원 그래픽 가속기의 구현)

  • Lee, Hyung;Park, Youn-Ok;Park, Jong-Won
    • Journal of Korea Multimedia Society
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    • v.3 no.5
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    • pp.526-534
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    • 2000
  • There have been many researches on the 3D graphic accelerator for high speed by needs of CAD/CAM,3D modeling, virtual reality or medical image. In this paper, an SIMD processor architecture for 3D graphic accelerator is proposed in order to improve the processing time of the 3D graphics, and a parallel Phong shading algorithm is presented to estimate performance of the proposed architecture. The proposed SIMD processor architecture for 3D graphic accelerator consists of PCI local bus interface, 16 Processing Elements (PE's), and Park's multi-access memory system (NAMS) that has 17 memory modules. A serial algorithm for Phong shading is modified for the architecture and the main key is to divide a polygon into $4\times{4}$ squares. And, for processing a square, 4 PE's are regarded as a PE Grou logically. Since MAMS can support block access type with interval 1, it is possible that 4 PE Groups process a square at a time. In consequence, 16 pixels are processed simultaneously. The proposed SIMD processor architecture is simulated by CADENCE Verilog-XL that is a package for the hardware simulation. With the same simulated results as that of the serial algorithm, the speed enhancement by the parallel algorithm to the serial one is 5.68.

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Design of Transformation Engine for Mobile 3D Graphics (모바일 3차원 그래픽을 위한 기하변환 엔진 설계)

  • Kim, Dae-Kyoung;Lee, Jee-Myong;Lee, Chan-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.10
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    • pp.49-54
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    • 2007
  • As digital contents based on 3D graphics are increased, the requirement for low power 3D graphic hardware for mobile devices is increased. We design a transformation engine for mobile 3D graphic processor. We propose a simplified transformation engine for mobile 3D graphic processor. The area of the transformation engine is reduced by merging a mapping transformation unit into a projective transformation unit and by replacing a clipping unit with a selection unit. It consists of a viewing transformation unit a projective transformation unit a divide by w nit, and a selection unit. It can process 32 bit floating point format of the IEEE-754 standard or a reduced 24 bit floating point format. It has a pipelined architecture so that a vertex is processed every 4 cycles except for the initial latency. The RTL code is verified using an FPGA.

Equi-Value Line Program Development for 3-Dimensional Finite Element Models using Personal Computer (개인용 컴퓨터를 이용한 3차원 유한요소 등가곡선 프로그램 개발)

  • Lee, Seok-Soon
    • Journal of the Korean Society for Precision Engineering
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    • v.9 no.1
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    • pp.44-52
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    • 1992
  • A post-processor is developed to be effectively usable in the personal computer. 3-dimensional controur lines are shown on the surface of the finite element model and also on the 3-dimensional cutting plane, using the function linearly interpolated onto the triangular elements which are constructed on the surface or sectional polygons. And these polygons are originated from the finite element model, 3-dimensional model is projected on the plane with hidden line removal by comparision technique[6]. The graphic data file is used to increase the protability of the program. It is easy to use in the other computer system if the graphic routine adopted that computer system is developed. The developed program has wide applications in 3-dimensional finite element analysis.

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DEVELOPMENT OF A POST-PROCESSING PROGRAM FOR VISUALIZATION OF MRI DATA (MRI Data 가시화용 후처리 프로그램 개발)

  • Myong, H.K.;Choi, H.H.
    • 한국전산유체공학회:학술대회논문집
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    • 2007.10a
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    • pp.67-72
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    • 2007
  • A post-processing program based on the OOP(Object-Oriented Programming) concept has been developed for visualization of MRI. User-friendly GUl(Graphic User Interface) has been built on the base of MFC(Microsoft Foundation Class). The program is organized as modules by classes based on VTK-library, and these classes are made to function through inheritance and cooperation which are an important and valuable concept of object-oriented programming. The major functions of this post-processor program are introduced and demonstrated, which include contour plot, surface plots, cut plot and clip plot as well as view manipulation (translation, rotation, scaling etc).

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An Implementation of User Interface Simulator dedicated to a Mobile Terminal (이동 단말기용 사용자 인터페이스 시뮬레이터 구현)

  • 이효상;허혜선;홍윤식
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.1049-1052
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    • 1999
  • We present a use. interface(UI) simulator for developing a mobile phone. This simulator consists of 3 major modules: Graphic Tool Editor, User Interface Software(UI), and Network Command Processor(NCP). The Graphic Tool Editor can design a virtual mobile terminal. The NCP sends a command to the phone and then receives its status from the phone after completion of the command. We can add or modify lots of features easily to the phone using the UI module. These modules can interact each other by sharing the common area in the memory. By doing so, these modules can exchange their status and data to operate in real-time. We have designed and tested a virtual prototyping phone for the LGP 3200 manufactured by LGIC by using the simulator. Through a series of experiment, we have believed that our virtual prototyping interactive simulator can do shorten its development and testing cycle by applying it in the early design phase.

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Economical Post-processing of Large Finite Element Model on Personal Computer (퍼스널 컴퓨터를 이용한 대형 유한요소 모델의 경제적인 그래픽 후처리)

  • 이성우;이선구;이태연
    • Proceedings of the Computational Structural Engineering Institute Conference
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    • 1989.10a
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    • pp.65-70
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    • 1989
  • Until recently post-processing of finite element model has been Heavily relied on expensive graphic peripheral devices. For this reason many engineers and researchers can not afford to access to the graphics. with the aid of inexpensive personal computers very econmical post-processor graphics program called MICRO-POST has been developed in conjunction with low-cost printers and plotters. Model geometry or results of analysis for the unlimitted meshes either produced by mainframe or microcomputer can be easily and economi-call presented in a number of different graphic devices. The paper presents the procedure obtaining the device the independent graphics, and the structure and functions of the program. It also describes a new error-preventive dialogue type input technique to control the plot operation in an interactive manner. Through the post-processing examples for the general purpose finite element programs, it demonstrates the usefulness of the program.

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A Design on Rasterizer for the verification in a 3D Graphic Processor (3D 그래픽 프로세서 검증을 위한 래스터라이저 설계)

  • Lee, Mi-Kyoung;Jang, Young Jo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2009.10a
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    • pp.639-642
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    • 2009
  • When the graphics accelerator for high-quality multimedia content design, hardware verification environment, easy and accurate performance evaluation in an embedded device is required. To work around this is not verified through the simulation waveform analysis to determine the actual calculated graphic images has designed a software rasterizer. Rasterizer is designed for Windows-based environment using the C language implementation of rasterization has a function at each step. Vertex data is entered and the results were verified.

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