• 제어로봇시스템학회논문지
• /
• 제5권1호
• /
• pp.33-38
• /
• 1999

This paper proposes a translation approach for PLCs (Programmable logic controllers) converting ladder diagrams directly to native codes, and describes detailed steps of the method followed by performance evaluation. A general-purpose DSP (Digital signal processor) based implementation validates the approach as well. A benchmark test shows that the Proposed translation framework fairly speeds up execution in comparison with the existing interpretation approach.

• 한국통신학회논문지
• /
• 제31권1C호
• /
• pp.46-54
• /
• 2006

The design method of synthetic aperture radar processor (SARP) in the critical design stage is to describe the processing algorithm, to estimate the fractional errors, and to set out the software (SW) and hardware (HW) mapping. The previous design methods for SARP are complex and depend on HW. Therefore, this paper proposes a critical design method that is of more general and independent of HW. This methodology can be applied for developing the space-based SARP using range-Doppler algorithm (RDA).

• 한국농공학회지
• /
• 제36권2호
• /
• pp.31-43
• /
• 1994

General concepts and overall procedures of interactive graphical user interface, a preand post- processor, for building analysis are introduced. Attention is forcused on the data structures and the modeling operators which can ensure the intergrity of its database should have. An example of model building process is presented to illustrate its capability, its facilities for modifying, and for processing.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1998년도 하계학술대회 논문집 G
• /
• pp.2402-2404
• /
• 1998

This paper proposes a translation method that converts ladder diagrams to binary executable codes for PLC (programmable logic controller)s. A PLC based on general purpose DSP(digital signal processor) validates the method. We performed a benchmark on the system that compares the execution time of the interpretation method and ours. Experimenal result shows how fast this method executes programs that consist of codes generated.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2001년도 하계종합학술대회 논문집(5)
• /
• pp.47-50
• /
• 2001

Nowadays ARM7 core is used in many fields such as PDA systems because of the low power and low cost. It is a general-purpose processor, designed for both efficient digital signal processing and controller operations. But the advent of the wireless communication creates a need for high computational performance for signal processing. And then This paper has been designed a floating-point multiplier compatible to IEEE-754 single precision format for ARMTTDMI performance improvement.

• 정보처리학회논문지C
• /
• 제11C권3호
• /
• pp.319-326
• /
• 2004

많은 공격과 네트워크 데이터 처리량이 증가하는 오늘날의 네트워크 수요를 NIDS가 유지시키기 위해 하드웨어 및 소프트웨어 시스템 구조에서 급진적 새로운 접근이 필요하다. 본 논문에서는 패킷 필터링과 트래픽 측정 뿐아니라 고의행위를 검출하는 패킷 페이로드 검열을 지원하는 네트워크 프로세서 기반의 인라인 모드 NIS를 제안하고, 특히 2한계 경색구조를 사용하여 심층 패킷 정열기능으로부터 펄터링과 측정기능을 분리한다 그래서 심층 패킷 검열기능의 복잡하고 시간소비 곽이 인라인 모드 시스템의 기본 기능을 멈추게 하거나 방해하지 않게 했다. 프로토타입 NP 기반의 NIDS는 PC 플랫폼에서 구현하였으므로 실험결과는 제안한 구조가 첫 단계에서 두개의 기가비트 포트의 전체 트래픽을 측정과 필터가 신뢰할 수 있음을 보였다. 일반목적 프로세스 기만의 검열 성능과 비교 가능한 두 번째 단계에서 실시간으로 320Mbps까지 패킷 페이로드를 주사할 수 있었다. 그러나 시뮬레이션에서 100bps APP 해법을 선택할 때 선로상 속도가 2Gbps까지 가능한 심층 패킷 검색 결과를 얻었다.

• 한국통신학회논문지
• /
• 제21권11호
• /
• pp.2966-2977
• /
• 1996

As design of very large circuits is made possible by rapid development of VLSI technologies, efficient fault simulation is needed. Ingeneral, fault simulation requires many computer resources. As general-purpose multiprocessors become more common and affordable, these seem to be an attractive and effective alternative for fault simulation. Efficient fault simulation of synchronous sequential circuits has been reported to be attainably by using a linear iterative array model for such a circuit, and combining parallel fault simulation with russogate fault simulation. Such fault simulation algorithm is parallelized on a general-purpose multiprocessor with shard memory for acceleration of fault simulation. Through the experimenal study, the effect of the number of processors on speed-up of simulation, processor utilization, and the effect of multiprocessor hardware on simulation performance are studied. Some results for experiments with benchmark circuits are shown.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2005년도 학술대회 논문집 정보 및 제어부문
• /
• pp.309-311
• /
• 2005

In general, for specific applications, customized hardware showed better performance than general processor in terms of processing time and power consumption. However, customized hardware systems have lacks of flexibility in nature and it leads the difficulties for debugging and architecture level revision for performance enhancement. To solve this problem, reconfigurable hardware is developed. Proposed reconfigurable hardware architecture for FIR filter system can easily change the architecture of filter blocks including filter tap size and their signal path. Proposed FIR filter architecture was implemented on FPGA using several MUXs and registers and it showed the reconfigurablility and reusability in several examples.

• 한국전산유체공학회지
• /
• 제12권2호
• /
• pp.32-36
• /
• 2007

NUFLEX is a general purpose program for the analysis 3D thermo/fluid flow and pre/post processor in a complex geometry. NUFLEX is composed of various physical models, such as phase change(solidification/melting) and spray, MHD(Magneto Hydraulic Dynamics) models. It is possible to simulate continuous cast iron process and spray droplet breakup/collision phenomenon. For the verification of these models, compared with the experimental data and commercial CFD code's results. The results show good agreements with experimental and comercial CFD codes's results.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 1992년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 19-21 Oct. 1992
• /
• pp.75-80
• /
• 1992

This paper deals with the design scheme of the custom control circuit for optimizing the interface of peripheral devices to general-purpose controllers for the high speed digital system. When the various peripheral devices such as memory, I/O devices and buffers which operate at low speed are interfaced to the microprocessor which operates at high speed, inserting the proper wait state to the processor is required. The proposed scheme designed with random logic may be applied to the high performance graphic system like the X-terminal. This circuit provides the flexibility and system independancy for the optimum digital system design.