• Journal of the Korea Institute of Military Science and Technology
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• v.20 no.4
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• pp.482-490
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• 2017

The radar signal processing procedure is divided into the pre-processing such as frequency down converting, down sampling, pulse compression, and etc, and the post-processing such as doppler filtering, extracting target information, detecting, tracking, and etc. The former is generally designed using FPGA because the procedure is relatively simple even though there are large amounts of ADC data to organize very quickly. On the other hand, in general, the latter is parallel processed by multiple DSPs because of complexity, flexibility and real-time processing. This paper presents the radar signal processor design using FPGA which includes not only the pre-processing but also the post-processing such as doppler filtering, bore-sight error, NCI(Non-Coherent Integration), CFAR(Constant False Alarm Rate) and etc.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.44-55
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• 2001

MAC(Multiply and ACcumulate) is the core operation of multimedia data processing. Because MAC units implemented on traditional DSP units or embedded processors have latency of three cycles and cannot operate on multiple data simultaneously, then, performances are seriously limited. Many high end general purpose microprocessors have SIMD MAC unit as a functional unit. But these high end MAC units must support pipeline structure for various operation modes and high clock frequency, which makes control logic complex and increases chip area. In this paper, a 64bit SIMD MAC unit for embedded processors is designed. It is implemented to have a latency of one clock cycle to remove pipeline control logics and a minimal area overhead for SIMD support is added to existing Booth multipliers.

• The KIPS Transactions:PartA
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• v.11A no.7 s.91
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• pp.537-546
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• 2004

In order to develop an application software for context-awareness techniques, we should program both all decisions on variable con-text-awareness and appropriate process with some program languages. These cause a loss of software production and unlimited repetition of program code. In this paper, we implement a context script language and language processor which can simplify a series of involved process acquired for context-awareness and describe them clearly. In addition, it can represent a definitions of context as standard syntax as well as accomplish them automatically. The proposed context script language provides functionality which can not only define efficiently a given context but also describe a variety of context with general purpose. Aiso, for the usefulness of the language processor, we build an application system which can provide music play service based on context-awareness.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.420-435
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• 2001

As multimedia technology has rapidly grown recently, many researches to process multimedia data efficiently using general-purpose processors have been studied. In this paper, we proposed multimedia instructions which can process multimedia data effectively, and suggested a processor architecture for those instructions. The processor was described with Verilog-HDL in the behavioral level and simulated with CADENCE$^{TM}$ tool. Proposed multimedia instructions are total 48 instructions which can be classified into 7 groups. Multimedia data have 64-bit format and are processed as parallel subwords of 8-bit 8 bytes, 16-bit 4 half words or 32-bit 2 words. Modeled processor is developed based on the Integer Unit of SPARC V.9. It has five-stage pipeline RISC architecture with Harvard principle.e.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.4
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• pp.233-239
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• 2015

This paper describes a method that is integrated trace for real-time virtualization environment. This method has solved the problem that the performance trace may not be able to analyze integrated method between heterogeneous operating systems which is consists of real-time operating systems and general-purpose operating system. In order to solve this problem, we have attempted to reuse the performance analysis function in general-purpose operating system, thereby real-time operating systems can be analyzed along with general-operating system. Furthermore, we have implemented a prototype based on ARM Cortex-A15 dual-core processor. By using this integrated trace method, real-time system developers can be improved productivity and reliability of results on real-time virtualization environment.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2882-2884
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• 2005

본 논문에서는 인터넷을 통한 멀티미디어 스트리밍 서비스 환경에서 다양한 표준으로 압축된 컨텐츠의 디코딩을 지원하기 위하여 general purpose DSP (Digital Signal Processor) 기반의 멀티미디어 서비스 플랫폼을 구현하였다. 다양한 표준 방식으로 압축된 멀티미디어 컨텐츠를 재생하기 위하여 Host 프로세서와 DSP 구조의 하드웨어를 설계하고, 멀티미디어 코덱을 DSP에 다운로드하는 소프트웨어적인 기법을 적용하였다. 설계한 플랫폼의 동작을 검증하기 위하여 리눅스 기반에서 DSP를 제어하는 네트워크 클라이언트 소프트웨어를 구현하고, Tl의 TMS 320C6416을 대상으로 구현한 MPEG-2 비디오와 AC-3 오디오 코덱을 적용하여 스트리밍 환경에서 멀티미디어 데이터가 원활하게 재생되는 것을 보였다.

• Journal of Power Electronics
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• v.7 no.2
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• pp.132-139
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• 2007

Electrical motors are an integral part of industrial plants with no less than 5 billion motors built world wide every year. The demand for low-cost brushless DC (BLDC) motors has increased in industrial applications. This paper presents a BLDC motor control algorithm for low-cost motor drive applications using general purpose microcontrollers which have only one on-chip timer. This paper describes how to realize pulse width modulation (PWM) signals with general input/output (I/O) ports to control a three-phase permanent magnet brushless DC motor using the timer interrupt on MSP430F1232.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.80-85
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• 2011

The mount of network traffic from the Internet is increasing because of the use of Broadband Convergence Networks(BcN). Network traffic is also increasing because of the development of application, especially multimedia traffic from IPTV, VOD, and online games. This multimedia traffic not only has a huge payload but also should be considered a threat in real time. For this reason, this study examines the ways that routers distribute the bandwidth in accordance to traffic properties. To classify the property of the traffic, it is essential to analyze the application layer. However, the general network processor architecture serially processes the L2-4 and L7 layer. We propose a novel parallel network processor architecture with a global cache that processes L2-4 and L7 in parallel. To verify the proposed architecture, we simulated both of the architecture with SystemC. EEMBC and SNORT was used to measure L2-4 and L7 processing time. When multimedia traffic was entered into the network processor in the same flow, the proposed architecture showed about 85% higher performance than general architecture.

• Journal of Life Science
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• v.15 no.2 s.69
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• pp.211-214
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• 2005

The studies were conducted to obtain basic informations on inheritance of some quantitative characters in kidney bean (Phaseolus vulgaris L.). Seven parents (Felibon, Renka, Processor, Kaboom, $BO_{22}$, Local variety $\#1$ and Local variety $\#2)$ and $F_1$ hybrids of 21 crosses from a set of diallel cross among varieties were used to estimate combining ability for eight agronomic characters such as days to flowering, days to maturity, stem length, pod numbers per plant, pod length, grain numbers per plant, 100-grain weight and grain weight per plant. General combining ability (GCA) and specific combining ability (SCA) were significantly different among all characters, and values of GCA were greater than those of SCA in all characters except number of grains per plant. In effect of GCA, Felibon expressed high GCA effect for days to flowering and number of grains per plant. Local variety $\#1$ showed high GCA effect for 100-grain weight and stem length. Local variety $\#2$appeared to high GCA effect for 100-grain weight and grain weight per plant. Processor expressed high GCA effect for days to maturity and grain weight per plant. Kaboom showed high GCA effect days to flowering and days to maturity. $BO_{22}$ appeared high GCA effect for all characters except for days to flowering, days to maturity and stem length. In the SCA effect, crosses of Felibonx Renka and Local variety $\#2{\times}Processor$ exhibited in high negative effect for days to flowering. Thus, these crosses were evaluated to useful for breeding early maturing variety. Crosses of breeding high yield variety were considered of $Felibon{\times}Local$ variety $\#1$, $Felibon{\times}Renka$ and Local variety $\#2{\times}BO_{22}$.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.2
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• pp.8-14
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• 1978

This paper discusses topics, which can be considered to generate a HANGEUL character pattern with general micro-processor.: A character must be composed by combining the input elements at their proper sizes and positions based on algorithm proposed here.